Dafenx d49c0f1f10 Emit Gen5 packed-integer and bit-count ops (#135) ...

Co-authored-by: Dafenx <196083014+Dafenxz0@users.noreply.github.com>

2026-07-14 17:10:40 +03:00

..

AgcExports.cs

Deadcell fix (#144)

2026-07-14 17:01:16 +03:00

Gen5ShaderIr.cs

[shader-decoder-part1] Implemented a shader decoder (Part 1) (#12)

2026-07-04 13:51:08 +03:00

Gen5ShaderMetadataReader.cs

[fixes] move repeating methods into CpuContext (#41)

2026-07-10 23:46:50 +03:00

Gen5ShaderScalarEvaluator.cs

[fixes] stackalloc warnings, consolidate duplicated methods, minor adjustments in project settings (#39)

2026-07-10 20:57:46 +03:00

Gen5ShaderTranslator.cs

[AGC] Decode gfx10 SOPP hint instructions (#108)

2026-07-14 00:28:47 +03:00

Gen5SpirvTranslator.Alu.cs

Emit Gen5 packed-integer and bit-count ops (#135)

2026-07-14 17:10:40 +03:00

Gen5SpirvTranslator.cs

[shader-decoder-part1-hotfix] New format support, maintenance8 support, robustness improvements, and bug fixes. This commit includes updates to the AGC exports, Gen5 SPIR-V translator, and Vulkan video presenter to enhance compatibility and performance. (#31)

2026-07-07 21:06:04 +03:00

GpuWaitRegistry.cs

[AGC] Quake rendering progress: WAIT_REG_MEM, draw fixes, VideoOut, and HLE improvements (#68)

2026-07-12 00:22:48 +03:00

SpirvFixedShaders.cs

[shader-decoder-part1] Implemented a shader decoder (Part 1) (#12)

2026-07-04 13:51:08 +03:00

SpirvModuleBuilder.cs

[shader-decoder-part1] Implemented a shader decoder (Part 1) (#12)

2026-07-04 13:51:08 +03:00