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Berk
e7149bf41f
* [shader] add scalar control flow graph * [shader] add gen5 branch resolver * [shader] add scalar reaching definitions * [shader] add cfg and dataflow tests * [shader] guard descriptors from unresolved registers
91 lines
3.0 KiB
C#
91 lines
3.0 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Collections.Generic;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Ir;
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using Xunit;
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namespace SharpEmu.ShaderCompiler.Tests;
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public sealed class Gen5ImplicitVccTests
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{
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private static Gen5ShaderInstruction Vopc(uint pc, string opcode = "VCmpEqU32") =>
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new(pc, Gen5ShaderEncoding.Vopc, opcode, [0u], [], [], null);
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private static Gen5ShaderInstruction Vop2(uint pc, string opcode) =>
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new(pc, Gen5ShaderEncoding.Vop2, opcode, [0u], [], [Gen5Operand.Vector(0)], null);
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private static Gen5ShaderInstruction Nop(uint pc) =>
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new(pc, Gen5ShaderEncoding.Sop1, "SNop", [0u], [], [], null);
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[Fact]
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public void VopcIsRecognisedAsAnImplicitVccWriter()
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{
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vopc(0)));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vopc(0, "VCmpLtF32")));
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}
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[Fact]
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public void Vop2CarryFormsAreRecognised()
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{
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VAddCoCiU32")));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VSubCoCiU32")));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VSubrevCoCiU32")));
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}
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[Fact]
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public void PlainVop2DoesNotWriteVcc()
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{
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Assert.False(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VAddF32")));
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Assert.False(Gen5ScalarSsa.WritesVccImplicitly(Nop(0)));
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}
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[Fact]
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public void VopcDefinesBothVccHalves()
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{
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List<Gen5ShaderInstruction> program = [Vopc(0), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var low = ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccLo);
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var high = ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccHi);
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Assert.Equal(IrReachingState.Single, low.State);
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Assert.Equal(0u, low.DefinitionPc);
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Assert.Equal(IrReachingState.Single, high.State);
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Assert.Equal(0u, high.DefinitionPc);
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}
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[Fact]
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public void WithoutTheImplicitWriteVccWouldLookUndefined()
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{
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// The regression this models: before implicit VCC was tracked the offset
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// register reported "none" and its stale value was used as a byte offset.
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List<Gen5ShaderInstruction> program = [Nop(0), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrReachingState.None, ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccLo).State);
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}
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[Fact]
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public void VccWrittenOnBothBranchesBecomesMultiple()
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{
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List<Gen5ShaderInstruction> program =
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[
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new(0, Gen5ShaderEncoding.Sopp, "SCbranchScc0", [2u], [], [], null),
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Vopc(4),
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new(8, Gen5ShaderEncoding.Sopp, "SBranch", [1u], [], [], null),
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Vopc(12),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(
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IrReachingState.Multiple,
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ssa.GetReachingDefinitionAt(16, Gen5ScalarSsa.VccLo).State);
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}
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}
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