mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-22 19:06:15 +08:00
João Victor Amorim
3005babab8
Completes the fused-FMA slice deferred by the VOP3P first slice (#145). v_pk_fma_f16 previously failed emission loudly because an f32 multiply-add followed by an f16 pack rounds twice; the pinned miss is fma(0x4100, 0x7522, 0x04EA) = 0x7A6B fused vs 0x7A6A via f32. The f32 product of two f16 values is exact, so only the addition needs correcting: compute sum = RN(product + addend), recover the exact residual with Knuth 2Sum, and if the sum is inexact with an even significand, step one ulp towards the true value. That is round-to-odd, and rounding the f32 result to f16 with round-to-nearest-even then matches a true fused f16 FMA exactly (24 significand bits >= 11 + 2). Inf/NaN inputs turn the residual into NaN, the ordered compare skips the parity fix, and IEEE special behaviour passes through unchanged. The op_sel/op_sel_hi/neg_lo/neg_hi source modifiers apply to src2 through the existing operand path; clamp stays rejected like the other packed ops. Every op in the 2Sum chain is decorated NoContraction: without it the AMD RDNA3 Windows driver folds the sequence, collapses the residual to zero, and the midpoint case decays to the double-rounded result. This was caught by running the emitted shader on a real device (see below). Verification: - A mirror of the emitted sequence was checked against an exact integer reference (every finite f16 is m * 2^-24, so a*b + c is an exact Int128 multiple of 2^-48, rounded once to f16 RNE) across 34M cases: directed midpoint pins, random sweeps over all operand classes, tiny-addend midpoint stress, subnormal products, and Inf/NaN propagation. 0 mismatches. - ShaderDump gains a pk-f16 program covering all five packed opcodes, both fma modifier paths, and the pinned constants; all programs decode and emit. - The executable exec program now computes the pinned fma and its negated-addend twin (0x7A6B7A6B / 0x7A6A7A6A, straddling an f16 midpoint) and stores them at offsets 20/24; GpuConformance checks both on device. All values match on an AMD Radeon RX 7700 XT.
367 lines
15 KiB
C#
367 lines
15 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Synthetic-shader conformance dumper.
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//
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// Feeds hand-assembled Gen5 (gfx10) instruction words through the real
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// decode -> SPIR-V pipeline (SharpEmu.ShaderCompiler + SharpEmu.ShaderCompiler.Vulkan)
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// and writes the resulting vertex, pixel, and compute SPIR-V blobs to disk. The blobs
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// can then be checked with spirv-val / spirv-dis.
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//
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// Programs that contain buffer_store_dword automatically get a single
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// global-memory binding covering every store, which the emitter exposes as
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// guestBuffers[0] (descriptor set 0, binding 0).
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//
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// Each program carries an expectation: ExpectTranslate=true programs must
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// decode and emit the requested stages; ExpectTranslate=false programs pin a decode
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// failure that must stay loud. Any unexpected outcome makes the tool exit
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// non-zero, so it can gate scripts/CI.
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//
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// Usage: SharpEmu.Tools.ShaderDump [output-directory]
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Vulkan;
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const ulong ProgramAddress = 0x100000;
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(string Name, bool ExpectTranslate, uint[] Words)[] testPrograms =
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[
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("fmac", true, [
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0x560A0501, // v_fmac_f32 v5, v1, v2
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0x580A0501, 0x42280000, // v_fmamk_f32 v5, v1, 42.0, v2
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0x5A0A0501, 0x42280000, // v_fmaak_f32 v5, v1, v2, 42.0
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0xD52B0005, 0x00020501, // v_fmac_f32_e64 v5, v1, v2
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0xBF810000, // s_endpgm
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]),
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("muls", true, [
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0xD5690005, 0x00020501, // v_mul_lo_u32 v5, v1, v2
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0xD56A0005, 0x00020501, // v_mul_hi_u32 v5, v1, v2
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0xD56B0005, 0x00020501, // v_mul_lo_i32 v5, v1, v2
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0xD56C0005, 0x00020501, // v_mul_hi_i32 v5, v1, v2
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0xBF810000, // s_endpgm
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]),
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// Packed f16 (VOP3P) arithmetic, including the fused multiply-add. The
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// constants pin the double-rounding regression from the VOP3P first slice:
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// fma(0x4100, 0x7522, 0x04EA) must round once to 0x7A6B (an f32
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// multiply-add then pack yields 0x7A6A). The last fma exercises the src2
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// neg_lo/neg_hi modifier path.
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("pk-f16", true, [
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0x7E0002FF, 0x41004100, // v_mov_b32 v0, 0x41004100 (2.5 packed)
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0x7E0202FF, 0x75227522, // v_mov_b32 v1, 0x75227522 (21024 packed)
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0x7E0402FF, 0x04EA04EA, // v_mov_b32 v2, 0x04EA04EA (~7.496e-5 packed)
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0xCC0E4003, 0x1C0A0300, // v_pk_fma_f16 v3, v0, v1, v2
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0xCC0F4004, 0x18020500, // v_pk_add_f16 v4, v0, v2
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0xCC104005, 0x18020300, // v_pk_mul_f16 v5, v0, v1
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0xCC114006, 0x18020300, // v_pk_min_f16 v6, v0, v1
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0xCC124007, 0x18020300, // v_pk_max_f16 v7, v0, v1
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0xCC0E4408, 0x9C0A0300, // v_pk_fma_f16 v8, v0, v1, neg_lo:[0,0,1] neg_hi:[0,0,1] v2
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0xBF810000, // s_endpgm
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]),
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("mrt", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x00000000, // v_mov_b32 v1, 0.0f
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0x7E0402FF, 0x00000000, // v_mov_b32 v2, 0.0f
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0x7E0602FF, 0x3F800000, // v_mov_b32 v3, 1.0f
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0x7E0802FF, 0x00000001, // v_mov_b32 v4, 1u
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0x7E0A02FF, 0x00000002, // v_mov_b32 v5, 2u
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0x7E0C02FF, 0x00000003, // v_mov_b32 v6, 3u
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0x7E0E02FF, 0x00000004, // v_mov_b32 v7, 4u
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0x7E1002FF, 0xFFFFFFFF, // v_mov_b32 v8, -1
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0x7E1202FF, 0x00000002, // v_mov_b32 v9, 2
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0x7E1402FF, 0xFFFFFFFD, // v_mov_b32 v10, -3
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0x7E1602FF, 0x00000004, // v_mov_b32 v11, 4
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800003F, 0x07060504, // exp mrt3 v4, v5, v6, v7
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0xF800086F, 0x0B0A0908, // exp mrt6 v8, v9, v10, v11 done
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0xBF810000, // s_endpgm
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]),
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("mrt-float2", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x3E800000, // v_mov_b32 v1, 0.25f
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0x7E0402FF, 0x3E800000, // v_mov_b32 v2, 0.25f
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0x7E0602FF, 0x3F000000, // v_mov_b32 v3, 0.5f
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800081F, 0x03020100, // exp mrt1 v0, v1, v2, v3 done
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0xBF810000, // s_endpgm
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]),
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("mrt8", true, [
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0x7E0002FF, 0x3F800000, // v_mov_b32 v0, 1.0f
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0x7E0202FF, 0x00000000, // v_mov_b32 v1, 0.0f
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0x7E0402FF, 0x00000000, // v_mov_b32 v2, 0.0f
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0x7E0602FF, 0x3F800000, // v_mov_b32 v3, 1.0f
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0xF800000F, 0x03020100, // exp mrt0 v0, v1, v2, v3
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0xF800001F, 0x03020100, // exp mrt1 v0, v1, v2, v3
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0xF800002F, 0x03020100, // exp mrt2 v0, v1, v2, v3
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0xF800003F, 0x03020100, // exp mrt3 v0, v1, v2, v3
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0xF800004F, 0x03020100, // exp mrt4 v0, v1, v2, v3
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0xF800005F, 0x03020100, // exp mrt5 v0, v1, v2, v3
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0xF800006F, 0x03020100, // exp mrt6 v0, v1, v2, v3
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0xF800087F, 0x03020100, // exp mrt7 v0, v1, v2, v3 done
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0xBF810000, // s_endpgm
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]),
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("mrt-partial", true, [
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0x7E0002FF, 0x3F4CCCCD, // v_mov_b32 v0, 0.8f
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0x7E0202FF, 0x3F333333, // v_mov_b32 v1, 0.7f
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0xF8000803, 0x03020100, // exp mrt0 v0, v1, off, off done
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0xBF810000, // s_endpgm
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]),
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("mrt-partial-merge", true, [
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0x7E0002FF, 0x3DCCCCCD, // v_mov_b32 v0, 0.1f
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0x7E0202FF, 0x3E4CCCCD, // v_mov_b32 v1, 0.2f
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0x7E0C02FF, 0x3E99999A, // v_mov_b32 v6, 0.3f
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0x7E0E02FF, 0x3ECCCCCD, // v_mov_b32 v7, 0.4f
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0xF8000003, 0x03020100, // exp mrt0 v0, v1, off, off
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0xF800080C, 0x07060504, // exp mrt0 off, off, v6, v7 done
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0xBF810000, // s_endpgm
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]),
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("sopp-hints", true, [
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0xBFA10001, // s_clause 0x1
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0xBFA30000, // s_waitcnt_depctr 0x0
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0xBF810000, // s_endpgm
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]),
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// s_round_mode / s_denorm_mode write the FP MODE state and must keep
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// failing decode loudly until their semantics are modeled (see #108);
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// this program pins that behavior.
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("sopp-mode", false, [
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0xBFA40000, // s_round_mode 0x0
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0xBFA50000, // s_denorm_mode 0x0
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0xBF810000, // s_endpgm
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]),
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// Executable end-to-end test: compute with real ALU instructions, then
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// buffer_store_dword results to guestBuffers[0] at offsets 0/4/8, prove
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// that a store with EXEC=0 does not land (offset 12 stays sentinel), and
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// that stores work again after EXEC is restored (offset 16). Offsets 20/24
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// hold the packed fused f16 FMA and its negated-addend twin, whose exact
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// results (0x7A6B7A6B / 0x7A6A7A6A) straddle an f16 midpoint and therefore
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// catch any double-rounding regression on real hardware.
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("exec", true, [
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0xBFA10001, // s_clause 0x1 (hint no-op in an executed program, needs #108)
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0x7E0002FF, 0x3FC00000, // v_mov_b32 v0, 1.5f
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0x7E0202FF, 0x40100000, // v_mov_b32 v1, 2.25f
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0x7E0402FF, 0x41200000, // v_mov_b32 v2, 10.0f
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0x56040300, // v_fmac_f32 v2, v0, v1 -> v2 = fma(1.5, 2.25, 10.0)
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0x7E0602FF, 0x7FFFFFFF, // v_mov_b32 v3, 0x7FFFFFFF
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0x7E0802FF, 0x00010003, // v_mov_b32 v4, 0x00010003
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0xD56C0005, 0x00020903, // v_mul_hi_i32 v5, v3, v4
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0xD56B0006, 0x00020903, // v_mul_lo_i32 v6, v3, v4
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0xE0700000, 0x80020200, // buffer_store_dword v2, off, s[8:11], 0
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0xE0700004, 0x80020500, // buffer_store_dword v5, off, s[8:11], 0 offset:4
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0xE0700008, 0x80020600, // buffer_store_dword v6, off, s[8:11], 0 offset:8
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0xBEFE0380, // s_mov_b32 exec_lo, 0 -> lane inactive
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0xE070000C, 0x80020200, // buffer_store_dword v2, off, s[8:11], 0 offset:12 (masked, must not land)
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0xBEFE03C1, // s_mov_b32 exec_lo, -1 -> lane active again
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0xE0700010, 0x80020000, // buffer_store_dword v0, off, s[8:11], 0 offset:16
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0x7E0E02FF, 0x41004100, // v_mov_b32 v7, 0x41004100 (2.5 packed)
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0x7E1002FF, 0x75227522, // v_mov_b32 v8, 0x75227522 (21024 packed)
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0x7E1202FF, 0x04EA04EA, // v_mov_b32 v9, 0x04EA04EA (~7.496e-5 packed)
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0xCC0E400A, 0x1C261107, // v_pk_fma_f16 v10, v7, v8, v9
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0xCC0E440B, 0x9C261107, // v_pk_fma_f16 v11, v7, v8, neg_lo:[0,0,1] neg_hi:[0,0,1] v9
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0xE0700014, 0x80020A00, // buffer_store_dword v10, off, s[8:11], 0 offset:20
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0xE0700018, 0x80020B00, // buffer_store_dword v11, off, s[8:11], 0 offset:24
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0xBF810000, // s_endpgm
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]),
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];
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var outputDirectory = args.Length > 0
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? args[0]
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: Path.Combine(AppContext.BaseDirectory, "spv");
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Directory.CreateDirectory(outputDirectory);
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var failures = 0;
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foreach (var (name, expectTranslate, words) in testPrograms)
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{
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var memory = new FakeMemory();
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memory.AddRegion(ProgramAddress, words);
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var ctx = new CpuContext(memory, Generation.Gen5);
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Console.WriteLine(
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$"[{name}] decode: " +
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Gen5ShaderTranslator.Describe(ctx, ProgramAddress, ProgramAddress));
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if (!Gen5ShaderTranslator.TryDecodeProgram(ctx, ProgramAddress, out var program, out var decodeError))
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{
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if (expectTranslate)
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{
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failures++;
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Console.WriteLine($"[{name}] FAILED: decode error ({decodeError})");
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}
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else
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{
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Console.WriteLine($"[{name}] decode failed as expected ({decodeError})");
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}
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continue;
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}
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if (!expectTranslate)
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{
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failures++;
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Console.WriteLine(
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$"[{name}] FAILED: decoded successfully but is pinned as a decode failure — " +
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"if the new decode support is intentional, its semantics need verifying here first");
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continue;
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}
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// Buffer stores need a global-memory binding; the emitter resolves them by
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// instruction PC, so collect store PCs from the decoded program itself.
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var storePcs = new List<uint>();
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foreach (var instruction in program!.Instructions)
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{
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if (instruction.Opcode.StartsWith("BufferStore", StringComparison.Ordinal))
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{
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storePcs.Add(instruction.Pc);
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}
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}
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// The binding's scalar base (8 -> s[8:11]) must match the srsrc field of
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// the hand-assembled buffer_store words, and the 64-byte backing store
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// must cover every hand-assembled store offset.
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var globalBindings = storePcs.Count > 0
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? new[]
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{
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new Gen5GlobalMemoryBinding(
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8u,
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0UL,
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storePcs,
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new byte[64],
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64,
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false),
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}
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: Array.Empty<Gen5GlobalMemoryBinding>();
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var state = new Gen5ShaderState(program, new uint[16], Metadata: null);
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var evaluation = new Gen5ShaderEvaluation(
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new uint[256],
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new uint[256],
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Array.Empty<Gen5ImageBinding>(),
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globalBindings);
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if (Gen5SpirvTranslator.TryCompileVertexShader(state, evaluation, out var vertexShader, out var vertexError))
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{
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var path = Path.Combine(outputDirectory, $"{name}.spv");
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File.WriteAllBytes(path, vertexShader.Spirv);
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Console.WriteLine($"[{name}] emit: success, {vertexShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] emit: FAILED ({vertexError})");
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}
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if (Gen5SpirvTranslator.TryCompileComputeShader(state, evaluation, 1, 1, 1, out var computeShader, out var computeError))
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{
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var path = Path.Combine(outputDirectory, $"{name}-cs.spv");
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File.WriteAllBytes(path, computeShader.Spirv);
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Console.WriteLine($"[{name}] compute emit: success, {computeShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] compute emit: FAILED ({computeError})");
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}
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if (name.StartsWith("mrt", StringComparison.Ordinal))
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{
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Gen5PixelOutputBinding[] pixelOutputs = name switch
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{
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"mrt" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 1, Gen5PixelOutputKind.Uint),
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new Gen5PixelOutputBinding(6, 2, Gen5PixelOutputKind.Sint),
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],
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"mrt-float2" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(1, 1, Gen5PixelOutputKind.Float),
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],
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"mrt8" =>
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(1, 1, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(2, 2, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 3, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(4, 4, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(5, 5, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(6, 6, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(7, 7, Gen5PixelOutputKind.Float),
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],
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_ => [new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float)],
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};
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if (Gen5SpirvTranslator.TryCompilePixelShader(state, evaluation, pixelOutputs, out var pixelShader, out var pixelError))
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{
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var path = Path.Combine(outputDirectory, $"{name}-ps.spv");
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File.WriteAllBytes(path, pixelShader.Spirv);
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Console.WriteLine($"[{name}] pixel emit: success, {pixelShader.Spirv.Length} bytes -> {path}");
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}
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else
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{
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failures++;
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Console.WriteLine($"[{name}] pixel emit: FAILED ({pixelError})");
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}
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if (name == "mrt")
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{
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Gen5PixelOutputBinding[] invalidOutputs =
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[
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new Gen5PixelOutputBinding(0, 0, Gen5PixelOutputKind.Float),
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new Gen5PixelOutputBinding(3, 7, Gen5PixelOutputKind.Float),
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];
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if (Gen5SpirvTranslator.TryCompilePixelShader(state, evaluation, invalidOutputs, out _, out var invalidError))
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{
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failures++;
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Console.WriteLine("[mrt] FAILED: sparse host locations were accepted");
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}
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else
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{
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Console.WriteLine($"[mrt] sparse host locations rejected as expected ({invalidError})");
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}
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}
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}
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}
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Console.WriteLine(failures == 0
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? "RESULT: all programs behaved as expected"
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: $"RESULT: {failures} unexpected outcome(s)");
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Environment.ExitCode = failures == 0 ? 0 : 1;
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internal sealed class FakeMemory : ICpuMemory
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{
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private readonly List<(ulong Base, byte[] Data)> _regions = [];
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public void AddRegion(ulong baseAddress, uint[] words)
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{
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var bytes = new byte[words.Length * sizeof(uint)];
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for (var index = 0; index < words.Length; index++)
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{
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BinaryPrimitives.WriteUInt32LittleEndian(
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bytes.AsSpan(index * sizeof(uint)),
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words[index]);
|
|
}
|
|
|
|
_regions.Add((baseAddress, bytes));
|
|
}
|
|
|
|
public bool TryRead(ulong virtualAddress, Span<byte> destination)
|
|
{
|
|
foreach (var (baseAddress, data) in _regions)
|
|
{
|
|
if (virtualAddress >= baseAddress &&
|
|
virtualAddress + (ulong)destination.Length <= baseAddress + (ulong)data.Length)
|
|
{
|
|
data.AsSpan(
|
|
(int)(virtualAddress - baseAddress),
|
|
destination.Length).CopyTo(destination);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public bool TryWrite(ulong virtualAddress, ReadOnlySpan<byte> source) => false;
|
|
}
|