mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-25 20:28:48 +08:00
fix(agc): merge Prospero attrib-table formats onto IR vertex inputs (#556)
IR-discovered BufferLoadFormat often keeps a stale float sharp format; patch DataFormat/offset from the AGC attrib table (semantic index), allow offen fetches, and map quirks 113/121 through NarrowVk for host vertex input. Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
MarcelMediaDev
@@ -6488,6 +6488,32 @@ public static partial class AgcExports
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TraceAstroTitlePixelGlobalProbe(pixelEvaluation);
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}
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// Patch BufferFormat from the attrib table onto the V# before host
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// vertex input. IR discovery often keeps a stale float format from the
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// unpatched sharp — that turns UI glyphs into gradient triangles.
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// Match by stride+offset (not bare base address) so interleaved streams
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// keep loading-video bindings intact.
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if (exportEvaluation.VertexInputs is { Count: > 0 } discoveredInputs &&
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AgcVertexMetadata.TryGetVertexTableRegisters(
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ctx,
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exportShaderAddress,
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exportShaderHeader,
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out var vertexTables))
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{
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var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
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ctx,
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exportEvaluation.ScalarRegisters,
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vertexTables,
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discoveredInputs);
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if (!ReferenceEquals(merged, discoveredInputs))
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{
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TraceAgcShader(
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$"agc.vertex_metadata_format es=0x{exportShaderAddress:X16} " +
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$"count={merged.Count}");
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exportEvaluation = exportEvaluation with { VertexInputs = merged };
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}
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}
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// Every bound color target the shader exports to. Deferred renderers
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// draw a multi-render-target G-buffer (up to eight slots) in one pass.
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// Fall back to slot 0 if we cannot match any export to a bound target.
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@@ -7269,6 +7295,7 @@ public static partial class AgcExports
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Mix(input.NumberFormat);
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Mix(input.Stride);
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Mix(input.OffsetBytes);
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Mix(input.PerInstance ? 1u : 0u);
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}
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}
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@@ -8277,7 +8304,8 @@ public static partial class AgcExports
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binding.OffsetBytes,
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binding.Data,
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binding.DataLength,
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binding.DataPooled);
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binding.DataPooled,
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binding.PerInstance);
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}
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return buffers;
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@@ -0,0 +1,788 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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namespace SharpEmu.Libs.Agc;
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/// <summary>
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/// AGC embedded vertex metadata. Locates
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/// PtrVertexBufferTable / PtrVertexAttribDescTable and builds authoritative
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/// attribute layouts that draw translation merges onto IR-discovered fetches.
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/// </summary>
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internal static class AgcVertexMetadata
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{
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private const ushort IllegalDirectOffset = 0xFFFF;
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private const ulong ShaderUserDataOffset = 0x08;
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private const ulong ShaderInputSemanticsOffset = 0x30;
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private const ulong ShaderNumInputSemanticsOffset = 0x50;
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internal enum AgcDirectResourceType : uint
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{
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PtrVertexBufferTable = 8,
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PtrVertexAttribDescTable = 10,
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Last = PtrVertexAttribDescTable,
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}
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internal readonly record struct VertexTableRegisters(
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int VertexBufferReg,
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int VertexAttribReg,
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uint InputSemanticsCount,
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ulong InputSemanticsAddress);
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/// <summary>
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/// One AGC attrib-table resource.
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/// Representation: <see cref="SharpBase"/> is the V# base; attribute byte
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/// offset is applied as <see cref="OffsetBytes"/> (Vulkan bind offset),
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/// not folded into the base — avoids double-counting when the IR prolog
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/// already bumped the sharp address.
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/// </summary>
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internal readonly record struct MetadataVertexResource(
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uint Location,
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uint Semantic,
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uint HardwareMapping,
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uint SizeInElements,
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ulong SharpBase,
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uint Stride,
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uint OffsetBytes,
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uint DataFormat,
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uint NumberFormat,
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uint ComponentCount,
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bool PerInstance);
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/// <summary>
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/// Reads AGC user-data direct-resource offsets for the ES header mapped to
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/// <paramref name="shaderCodeAddress"/>. Returns false when the header is
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/// unknown or the tables are absent (attribute-less clears).
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/// </summary>
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internal static bool TryGetVertexTableRegisters(
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CpuContext ctx,
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ulong shaderCodeAddress,
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ulong shaderHeaderAddress,
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out VertexTableRegisters registers)
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{
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registers = new VertexTableRegisters(-1, -1, 0, 0);
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if (shaderHeaderAddress == 0 ||
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!TryReadUInt64(ctx, shaderHeaderAddress + ShaderUserDataOffset, out var userDataAddress) ||
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userDataAddress == 0)
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{
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return false;
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}
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// ShaderUserData layout:
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// 0x00: uint16_t* direct_resource_offset
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// 0x08: sharp_resource_offset[4]
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// 0x28: eud_size_dw, srt_size_dw
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// 0x2C: direct_resource_count
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if (!TryReadUInt64(ctx, userDataAddress, out var directResourceOffset) ||
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!TryReadUInt16(ctx, userDataAddress + 0x2C, out var directResourceCount))
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{
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return false;
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}
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var maxTypes = (uint)AgcDirectResourceType.Last + 1u;
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if (directResourceCount > maxTypes || directResourceOffset == 0)
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{
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return false;
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}
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var vertexBufferReg = -1;
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var vertexAttribReg = -1;
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for (uint type = 0; type < directResourceCount; type++)
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{
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if (!TryReadUInt16(
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ctx,
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directResourceOffset + (type * sizeof(ushort)),
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out var reg) ||
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reg == IllegalDirectOffset)
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{
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continue;
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}
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switch ((AgcDirectResourceType)type)
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{
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case AgcDirectResourceType.PtrVertexBufferTable:
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vertexBufferReg = reg;
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break;
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case AgcDirectResourceType.PtrVertexAttribDescTable:
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vertexAttribReg = reg;
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break;
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}
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}
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if (vertexBufferReg < 0 || vertexAttribReg < 0)
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{
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return false;
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}
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if (!TryReadUInt64(
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ctx,
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shaderHeaderAddress + ShaderInputSemanticsOffset,
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out var inputSemanticsAddress) ||
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!TryReadUInt32(
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ctx,
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shaderHeaderAddress + ShaderNumInputSemanticsOffset,
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out var inputSemanticsCount) ||
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inputSemanticsCount == 0 ||
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inputSemanticsAddress == 0)
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{
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return false;
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}
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registers = new VertexTableRegisters(
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vertexBufferReg,
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vertexAttribReg,
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inputSemanticsCount,
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inputSemanticsAddress);
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return true;
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}
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/// <summary>
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/// Builds attrib resources from AGC input_semantics + tables.
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/// ShaderSemantic packing:
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/// bits [7:0] semantic → attrib table index
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/// bits [15:8] hardware_mapping → VGPR destination
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/// bits [19:16] size_in_elements
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/// </summary>
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internal static bool TryBuildVertexResourcesFromMetadata(
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CpuContext ctx,
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IReadOnlyList<uint> scalarRegisters,
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VertexTableRegisters tables,
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out IReadOnlyList<MetadataVertexResource> resources)
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{
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resources = Array.Empty<MetadataVertexResource>();
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if (tables.VertexAttribReg < 0 ||
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tables.VertexBufferReg < 0 ||
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tables.VertexAttribReg + 1 >= scalarRegisters.Count ||
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tables.VertexBufferReg + 1 >= scalarRegisters.Count ||
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tables.InputSemanticsCount == 0)
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{
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return false;
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}
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var attribTable =
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((ulong)scalarRegisters[tables.VertexAttribReg + 1] << 32) |
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scalarRegisters[tables.VertexAttribReg];
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var bufferTable =
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((ulong)scalarRegisters[tables.VertexBufferReg + 1] << 32) |
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scalarRegisters[tables.VertexBufferReg];
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if (attribTable == 0 || bufferTable == 0)
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{
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return false;
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}
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var built = new List<MetadataVertexResource>((int)tables.InputSemanticsCount);
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for (uint i = 0; i < tables.InputSemanticsCount; i++)
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{
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if (!TryReadUInt32(
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ctx,
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tables.InputSemanticsAddress + (i * sizeof(uint)),
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out var semanticWord))
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{
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return false;
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}
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// Attrib index is semantic bits [7:0], not hardware_mapping.
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var semantic = semanticWord & 0xFFu;
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var hardwareMapping = (semanticWord >> 8) & 0xFFu;
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var sizeInElements = (semanticWord >> 16) & 0xFu;
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if (!TryReadUInt32(ctx, attribTable + (semantic * sizeof(uint)), out var attribWord))
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{
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return false;
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}
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// Attrib dword: buffer index [4:0], format [13:5], offset [25:14], fetch [26].
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var bufferIndex = attribWord & 0x1Fu;
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var format = (attribWord >> 5) & 0x1FFu;
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var offset = (attribWord >> 14) & 0xFFFu;
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var fetchIndex = (attribWord >> 26) & 0x1u;
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var sharpAddress = bufferTable + (bufferIndex * 16u);
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if (!TryReadUInt32(ctx, sharpAddress, out var sharp0) ||
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!TryReadUInt32(ctx, sharpAddress + 4, out var sharp1))
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{
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return false;
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}
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var sharpBase = sharp0 | ((ulong)(sharp1 & 0xFFFFu) << 32);
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var stride = (sharp1 >> 16) & 0x3FFFu;
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if (sharpBase == 0 || stride == 0)
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{
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continue;
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}
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var fallbackComponents = sizeInElements != 0 ? sizeInElements : 4u;
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var (dataFormat, numberFormat, components) =
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MapAttribFormat(format, fallbackComponents);
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built.Add(new MetadataVertexResource(
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Location: i,
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Semantic: semantic,
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HardwareMapping: hardwareMapping,
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SizeInElements: sizeInElements,
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SharpBase: sharpBase,
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Stride: stride,
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OffsetBytes: offset,
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DataFormat: dataFormat,
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NumberFormat: numberFormat,
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ComponentCount: components,
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PerInstance: fetchIndex != 0));
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}
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if (built.Count == 0)
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{
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return false;
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}
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resources = built;
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return true;
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}
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/// <summary>
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/// Patch IR-discovered fetches from the attrib table onto the V# format/offset.
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/// Prefer 1:1 Location pairing when counts match on one interleaved stream
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/// (GTA UI glyphs). Otherwise match by stride + byte offset. Never rebases
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/// BaseAddress/Data/Location/Pc/PerInstance.
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/// </summary>
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internal static IReadOnlyList<Gen5VertexInputBinding> MergeVertexInputsFromMetadata(
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CpuContext ctx,
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IReadOnlyList<uint> scalarRegisters,
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VertexTableRegisters tables,
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IReadOnlyList<Gen5VertexInputBinding> discovered)
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{
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if (discovered.Count == 0 ||
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!TryBuildVertexResourcesFromMetadata(
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ctx,
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scalarRegisters,
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tables,
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out var resources))
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{
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return discovered;
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}
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if (TryMergeByLocationPairing(discovered, resources, out var paired))
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{
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return paired;
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}
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var merged = new List<Gen5VertexInputBinding>(discovered.Count);
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var usedResources = new bool[resources.Count];
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var changed = false;
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foreach (var input in discovered)
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{
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if (!TryMatchMetadataResource(input, resources, usedResources, out var resource, out var fillOffset))
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{
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merged.Add(input);
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continue;
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}
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var refined = ApplyMetadataFormat(input, resource, fillOffset);
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changed |= refined != input;
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merged.Add(refined);
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}
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return changed ? merged : discovered;
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}
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/// <summary>
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/// When discovery and metadata describe the same interleaved stream with
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/// equal attribute counts, pair by sorted Location (semantic order).
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/// Keeps each binding's Pc/Location for SPIR-V; overlays format + offset.
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/// </summary>
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private static bool TryMergeByLocationPairing(
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IReadOnlyList<Gen5VertexInputBinding> discovered,
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IReadOnlyList<MetadataVertexResource> resources,
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out IReadOnlyList<Gen5VertexInputBinding> merged)
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{
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merged = discovered;
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if (discovered.Count != resources.Count || discovered.Count == 0)
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{
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return false;
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}
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var orderedInputs = discovered.OrderBy(static input => input.Location).ToArray();
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var orderedResources = resources.OrderBy(static resource => resource.Location).ToArray();
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var streamBase = orderedResources[0].SharpBase;
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var streamStride = orderedResources[0].Stride;
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for (var index = 0; index < orderedResources.Length; index++)
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{
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var resource = orderedResources[index];
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var input = orderedInputs[index];
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if (resource.SharpBase != streamBase ||
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resource.Stride != streamStride ||
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(input.Stride != 0 && input.Stride != streamStride) ||
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!IsSameVertexStream(input, resource))
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{
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return false;
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}
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}
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var byPc = new Dictionary<uint, Gen5VertexInputBinding>(discovered.Count);
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var changed = false;
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for (var index = 0; index < orderedInputs.Length; index++)
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{
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var input = orderedInputs[index];
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var resource = orderedResources[index];
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var fillOffset = input.BaseAddress == resource.SharpBase ||
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IsAddressInsideCapturedSpan(input, resource.SharpBase);
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var refined = ApplyMetadataFormat(input, resource, fillOffset);
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changed |= refined != input;
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byPc[input.Pc] = refined;
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}
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|
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if (!changed)
|
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{
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return false;
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}
|
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|
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var result = new Gen5VertexInputBinding[discovered.Count];
|
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for (var index = 0; index < discovered.Count; index++)
|
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{
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result[index] = byPc[discovered[index].Pc];
|
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}
|
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|
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merged = result;
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return true;
|
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}
|
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|
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private static Gen5VertexInputBinding ApplyMetadataFormat(
|
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Gen5VertexInputBinding input,
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MetadataVertexResource resource,
|
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bool fillOffsetBytes)
|
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{
|
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var components = input.ComponentCount != 0 &&
|
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input.ComponentCount < resource.ComponentCount
|
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? input.ComponentCount
|
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: resource.ComponentCount;
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|
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return input with
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{
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DataFormat = resource.DataFormat,
|
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NumberFormat = resource.NumberFormat,
|
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ComponentCount = components,
|
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OffsetBytes = fillOffsetBytes ? resource.OffsetBytes : input.OffsetBytes,
|
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};
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Legacy entry point — forwards to <see cref="MergeVertexInputsFromMetadata"/>.
|
||||
/// </summary>
|
||||
internal static IReadOnlyList<Gen5VertexInputBinding> RefineVertexInputs(
|
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CpuContext ctx,
|
||||
IReadOnlyList<uint> scalarRegisters,
|
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VertexTableRegisters tables,
|
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IReadOnlyList<Gen5VertexInputBinding> discovered) =>
|
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MergeVertexInputsFromMetadata(ctx, scalarRegisters, tables, discovered);
|
||||
|
||||
/// <summary>
|
||||
/// Collects SBufferLoad / SLoad PCs that read the AGC attrib or buffer
|
||||
/// tables (embedded-fetch prolog). Those loads are executed on the
|
||||
/// CPU during scalar evaluation; once vertex inputs are bound they must
|
||||
/// not run again as live SSBOs on the GPU.
|
||||
/// </summary>
|
||||
internal static HashSet<uint> CollectFetchPrologPcs(
|
||||
Gen5ShaderProgram program,
|
||||
VertexTableRegisters tables)
|
||||
{
|
||||
var pcs = new HashSet<uint>();
|
||||
if (tables.VertexAttribReg < 0 || tables.VertexBufferReg < 0)
|
||||
{
|
||||
return pcs;
|
||||
}
|
||||
|
||||
var tableRegs = new HashSet<uint>
|
||||
{
|
||||
(uint)tables.VertexAttribReg,
|
||||
(uint)tables.VertexAttribReg + 1u,
|
||||
(uint)tables.VertexBufferReg,
|
||||
(uint)tables.VertexBufferReg + 1u,
|
||||
};
|
||||
|
||||
foreach (var instruction in program.Instructions)
|
||||
{
|
||||
var isScalarLoad =
|
||||
instruction.Opcode.StartsWith("SBufferLoad", StringComparison.Ordinal) ||
|
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instruction.Opcode.StartsWith("SLoad", StringComparison.Ordinal);
|
||||
if (!isScalarLoad)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// SMEM loads encode the scalar base pointer in Sources[0].
|
||||
if (instruction.Sources.Count > 0 &&
|
||||
instruction.Sources[0] is
|
||||
{
|
||||
Kind: Gen5OperandKind.ScalarRegister,
|
||||
Value: var scalarBase,
|
||||
} &&
|
||||
tableRegs.Contains(scalarBase))
|
||||
{
|
||||
pcs.Add(instruction.Pc);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (instruction.Control is Gen5BufferMemoryControl buffer &&
|
||||
tableRegs.Contains(buffer.ScalarResource))
|
||||
{
|
||||
pcs.Add(instruction.Pc);
|
||||
}
|
||||
}
|
||||
|
||||
return pcs;
|
||||
}
|
||||
|
||||
private static bool TryMatchMetadataResource(
|
||||
Gen5VertexInputBinding input,
|
||||
IReadOnlyList<MetadataVertexResource> resources,
|
||||
bool[] usedResources,
|
||||
out MetadataVertexResource resource,
|
||||
out bool fillOffsetBytes)
|
||||
{
|
||||
resource = default;
|
||||
fillOffsetBytes = false;
|
||||
var bestScore = int.MinValue;
|
||||
var bestIndex = -1;
|
||||
var bestFillOffset = false;
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (usedResources[index])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
var candidate = resources[index];
|
||||
if (candidate.Stride != 0 &&
|
||||
input.Stride != 0 &&
|
||||
candidate.Stride != input.Stride)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!IsSameVertexStream(input, candidate))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
var attrAddress = candidate.SharpBase + candidate.OffsetBytes;
|
||||
var score = int.MinValue;
|
||||
var fillOffset = false;
|
||||
|
||||
// Post-capture interleaved: shared BaseAddress, distinct OffsetBytes.
|
||||
if (input.OffsetBytes == candidate.OffsetBytes &&
|
||||
(input.BaseAddress == candidate.SharpBase ||
|
||||
IsAddressInsideCapturedSpan(input, candidate.SharpBase)))
|
||||
{
|
||||
score = 400;
|
||||
}
|
||||
// IR prolog baked attrib offset into the V# base.
|
||||
else if (input.BaseAddress == attrAddress)
|
||||
{
|
||||
score = 350;
|
||||
}
|
||||
// Discovery never saw the attrib offset — only safe when this
|
||||
// resource's offset uniquely identifies it among unused entries.
|
||||
else if (input.BaseAddress == candidate.SharpBase &&
|
||||
input.OffsetBytes == 0 &&
|
||||
candidate.OffsetBytes != 0 &&
|
||||
IsUniqueUnusedOffset(resources, usedResources, candidate.OffsetBytes, index))
|
||||
{
|
||||
score = 300;
|
||||
fillOffset = true;
|
||||
}
|
||||
else if (input.BaseAddress == candidate.SharpBase &&
|
||||
input.OffsetBytes == 0 &&
|
||||
candidate.OffsetBytes == 0)
|
||||
{
|
||||
score = 250;
|
||||
}
|
||||
|
||||
if (score > bestScore)
|
||||
{
|
||||
bestScore = score;
|
||||
bestIndex = index;
|
||||
bestFillOffset = fillOffset;
|
||||
}
|
||||
}
|
||||
|
||||
// Require an offset-aware match. Bare SharpBase ties (score 250) are
|
||||
// only accepted when a single unused resource remains for that stream.
|
||||
if (bestIndex < 0 || bestScore < 300)
|
||||
{
|
||||
if (bestIndex < 0 || bestScore < 250)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
var unusedSameStream = 0;
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (!usedResources[index] && IsSameVertexStream(input, resources[index]))
|
||||
{
|
||||
unusedSameStream++;
|
||||
}
|
||||
}
|
||||
|
||||
if (unusedSameStream != 1)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
usedResources[bestIndex] = true;
|
||||
resource = resources[bestIndex];
|
||||
fillOffsetBytes = bestFillOffset;
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool IsSameVertexStream(
|
||||
Gen5VertexInputBinding input,
|
||||
MetadataVertexResource resource)
|
||||
{
|
||||
if (input.BaseAddress == resource.SharpBase ||
|
||||
input.BaseAddress == resource.SharpBase + resource.OffsetBytes)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
return IsAddressInsideCapturedSpan(input, resource.SharpBase);
|
||||
}
|
||||
|
||||
private static bool IsAddressInsideCapturedSpan(
|
||||
Gen5VertexInputBinding input,
|
||||
ulong address) =>
|
||||
input.DataLength > 0 &&
|
||||
address >= input.BaseAddress &&
|
||||
address < input.BaseAddress + (ulong)input.DataLength;
|
||||
|
||||
private static bool IsUniqueUnusedOffset(
|
||||
IReadOnlyList<MetadataVertexResource> resources,
|
||||
bool[] usedResources,
|
||||
uint offsetBytes,
|
||||
int candidateIndex)
|
||||
{
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (index == candidateIndex || usedResources[index])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (resources[index].OffsetBytes == offsetBytes)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Attrib-table format
|
||||
/// fields are VertexAttribFormat; V# / Vulkan paths need BufferFormat.
|
||||
/// Unknown values pass through (already BufferFormat).
|
||||
/// </summary>
|
||||
private static uint VertexAttribFormatToBufferFormat(uint format) =>
|
||||
format switch
|
||||
{
|
||||
0 => 0, // Invalid
|
||||
4 => 1, // k8UNorm
|
||||
8 => 2, // k8SNorm
|
||||
12 => 3, // k8UScaled
|
||||
16 => 4, // k8SScaled
|
||||
20 => 5, // k8UInt
|
||||
24 => 6, // k8SInt
|
||||
28 => 7, // k16UNorm
|
||||
32 => 8, // k16SNorm
|
||||
36 => 9, // k16UScaled
|
||||
40 => 10, // k16SScaled
|
||||
44 => 11, // k16UInt
|
||||
48 => 12, // k16SInt
|
||||
52 => 13, // k16Float
|
||||
57 => 14, // k8_8UNorm
|
||||
61 => 15, // k8_8SNorm
|
||||
65 => 16, // k8_8UScaled
|
||||
69 => 17, // k8_8SScaled
|
||||
73 => 18, // k8_8UInt
|
||||
77 => 19, // k8_8SInt
|
||||
80 => 20, // k32UInt
|
||||
84 => 21, // k32SInt
|
||||
88 => 22, // k32Float
|
||||
93 => 23, // k16_16UNorm
|
||||
97 => 24, // k16_16SNorm
|
||||
101 => 25, // k16_16UScaled
|
||||
105 => 26, // k16_16SScaled
|
||||
109 => 27, // k16_16UInt
|
||||
113 => 28, // k16_16SInt
|
||||
117 => 29, // k16_16Float
|
||||
122 => 30, // k11_11_10UNorm
|
||||
126 => 31,
|
||||
130 => 32,
|
||||
134 => 33,
|
||||
138 => 34,
|
||||
142 => 35,
|
||||
146 => 36,
|
||||
150 => 37, // k10_11_11UNorm
|
||||
154 => 38,
|
||||
158 => 39,
|
||||
162 => 40,
|
||||
166 => 41,
|
||||
170 => 42,
|
||||
174 => 43,
|
||||
179 => 44, // k2_10_10_10UNorm
|
||||
183 => 45,
|
||||
187 => 46,
|
||||
191 => 47,
|
||||
195 => 48,
|
||||
199 => 49,
|
||||
203 => 50, // k10_10_10_2UNorm
|
||||
207 => 51,
|
||||
211 => 52,
|
||||
215 => 53,
|
||||
219 => 54,
|
||||
223 => 55,
|
||||
227 => 56, // k8_8_8_8UNorm
|
||||
231 => 57,
|
||||
235 => 58,
|
||||
239 => 59,
|
||||
243 => 60,
|
||||
247 => 61,
|
||||
249 => 62, // k32_32UInt
|
||||
253 => 63,
|
||||
257 => 64, // k32_32Float
|
||||
263 => 65, // k16_16_16_16UNorm
|
||||
267 => 66,
|
||||
271 => 67,
|
||||
275 => 68,
|
||||
279 => 69,
|
||||
283 => 70,
|
||||
287 => 71, // k16_16_16_16Float
|
||||
290 => 72, // k32_32_32UInt
|
||||
294 => 73,
|
||||
298 => 74,
|
||||
303 => 75, // k32_32_32_32UInt
|
||||
307 => 76,
|
||||
311 => 77, // k32_32_32_32Float
|
||||
_ => format,
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Maps Prospero attrib-table formats onto GNM (DataFormat, NumberFormat,
|
||||
/// Components) for <c>ToVkVertexFormat</c>. Accepts VertexAttribFormat
|
||||
/// or BufferFormat (pass-through). NumberFormat: 0 Unorm, 1 SNorm,
|
||||
/// 2 UScaled, 3 SScaled, 4 UInt, 5 SInt, 7 Float.
|
||||
/// </summary>
|
||||
private static (uint DataFormat, uint NumberFormat, uint Components) MapAttribFormat(
|
||||
uint attribFormat,
|
||||
uint fallbackComponents)
|
||||
{
|
||||
// Prospero VertexAttribFormat quirks before BufferFormat conversion.
|
||||
if (attribFormat == 113)
|
||||
{
|
||||
return (14, 7, 4); // R32G32B32A32_SFLOAT
|
||||
}
|
||||
|
||||
if (attribFormat == 121)
|
||||
{
|
||||
return (5, 7, 2); // R16G16_SFLOAT
|
||||
}
|
||||
|
||||
var bufferFormat = VertexAttribFormatToBufferFormat(attribFormat);
|
||||
|
||||
// Prospero::BufferFormat numeric values (gpu_defs.h).
|
||||
return bufferFormat switch
|
||||
{
|
||||
1 => (1, 0, 1), // k8UNorm
|
||||
2 => (1, 1, 1), // k8SNorm
|
||||
3 => (1, 2, 1), // k8UScaled
|
||||
4 => (1, 3, 1), // k8SScaled
|
||||
5 => (1, 4, 1), // k8UInt
|
||||
6 => (1, 5, 1), // k8SInt
|
||||
7 => (2, 0, 1), // k16UNorm
|
||||
8 => (2, 1, 1), // k16SNorm
|
||||
9 => (2, 2, 1), // k16UScaled
|
||||
10 => (2, 3, 1), // k16SScaled
|
||||
11 => (2, 4, 1), // k16UInt
|
||||
12 => (2, 5, 1), // k16SInt
|
||||
13 => (2, 7, 1), // k16Float
|
||||
14 => (3, 0, 2), // k8_8UNorm
|
||||
15 => (3, 1, 2), // k8_8SNorm
|
||||
16 => (3, 2, 2), // k8_8UScaled
|
||||
17 => (3, 3, 2), // k8_8SScaled
|
||||
18 => (3, 4, 2), // k8_8UInt
|
||||
19 => (3, 5, 2), // k8_8SInt
|
||||
20 => (4, 4, 1), // k32UInt
|
||||
21 => (4, 5, 1), // k32SInt
|
||||
22 => (4, 7, 1), // k32Float
|
||||
23 => (5, 0, 2), // k16_16UNorm
|
||||
24 => (5, 1, 2), // k16_16SNorm
|
||||
25 => (5, 2, 2), // k16_16UScaled
|
||||
26 => (5, 3, 2), // k16_16SScaled
|
||||
27 => (5, 4, 2), // k16_16UInt
|
||||
28 => (5, 5, 2), // k16_16SInt
|
||||
29 => (5, 7, 2), // k16_16Float
|
||||
50 => (9, 0, 4), // k10_10_10_2UNorm
|
||||
51 => (9, 1, 4), // k10_10_10_2SNorm
|
||||
56 => (10, 0, 4), // k8_8_8_8UNorm
|
||||
57 => (10, 1, 4), // k8_8_8_8SNorm
|
||||
58 => (10, 2, 4), // k8_8_8_8UScaled
|
||||
59 => (10, 3, 4), // k8_8_8_8SScaled
|
||||
60 => (10, 4, 4), // k8_8_8_8UInt
|
||||
61 => (10, 5, 4), // k8_8_8_8SInt
|
||||
62 => (11, 4, 2), // k32_32UInt
|
||||
63 => (11, 5, 2), // k32_32SInt
|
||||
64 => (11, 7, 2), // k32_32Float
|
||||
65 => (12, 0, 4), // k16_16_16_16UNorm
|
||||
66 => (12, 1, 4), // k16_16_16_16SNorm
|
||||
67 => (12, 2, 4), // k16_16_16_16UScaled
|
||||
68 => (12, 3, 4), // k16_16_16_16SScaled
|
||||
69 => (12, 4, 4), // k16_16_16_16UInt
|
||||
70 => (12, 5, 4), // k16_16_16_16SInt
|
||||
71 => (12, 7, 4), // k16_16_16_16Float
|
||||
72 => (13, 4, 3), // k32_32_32UInt
|
||||
73 => (13, 5, 3), // k32_32_32SInt
|
||||
74 => (13, 7, 3), // k32_32_32Float
|
||||
75 => (14, 4, 4), // k32_32_32_32UInt
|
||||
76 => (14, 5, 4), // k32_32_32_32SInt
|
||||
77 => (14, 7, 4), // k32_32_32_32Float
|
||||
_ => (14, 7, Math.Clamp(fallbackComponents, 1u, 4u)),
|
||||
};
|
||||
}
|
||||
|
||||
private static bool TryReadUInt16(CpuContext ctx, ulong address, out ushort value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[2];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt16LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool TryReadUInt32(CpuContext ctx, ulong address, out uint value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[4];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt32LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool TryReadUInt64(CpuContext ctx, ulong address, out ulong value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[8];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt64LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -76,7 +76,8 @@ internal sealed record GuestVertexBuffer(
|
||||
uint OffsetBytes,
|
||||
byte[] Data,
|
||||
int Length,
|
||||
bool Pooled);
|
||||
bool Pooled,
|
||||
bool PerInstance = false);
|
||||
|
||||
internal sealed record GuestIndexBuffer(
|
||||
byte[] Data,
|
||||
|
||||
@@ -1225,8 +1225,11 @@ internal static partial class MetalVideoPresenter
|
||||
? vertexBuffer.Stride
|
||||
: Math.Max(vertexBuffer.ComponentCount, 1) * 4;
|
||||
MetalNative.Send(layout, MetalNative.Selector("setStride:"), (nint)stride);
|
||||
// MTLVertexStepFunction.PerVertex = 1.
|
||||
MetalNative.Send(layout, MetalNative.Selector("setStepFunction:"), 1);
|
||||
// MTLVertexStepFunction: PerVertex = 1, PerInstance = 2.
|
||||
MetalNative.Send(
|
||||
layout,
|
||||
MetalNative.Selector("setStepFunction:"),
|
||||
vertexBuffer.PerInstance ? 2 : 1);
|
||||
}
|
||||
|
||||
return descriptor;
|
||||
|
||||
@@ -3170,6 +3170,7 @@ internal static unsafe class VulkanVideoPresenter
|
||||
public uint NumberFormat;
|
||||
public uint Stride;
|
||||
public uint OffsetBytes;
|
||||
public bool PerInstance;
|
||||
}
|
||||
|
||||
private const Format DepthFormat = Format.D32Sfloat;
|
||||
@@ -6658,33 +6659,47 @@ internal static unsafe class VulkanVideoPresenter
|
||||
PName = entryPoint,
|
||||
};
|
||||
|
||||
var vertexBindingDescriptions =
|
||||
new VertexInputBindingDescription[resources.VertexBuffers.Length];
|
||||
// One Vulkan binding per unique host buffer and input rate
|
||||
// (fetch_index). Attributes share that binding with
|
||||
// Offset = OffsetBytes.
|
||||
var bindingByBuffer = new Dictionary<(ulong Handle, bool PerInstance), uint>();
|
||||
var vertexBindingList = new List<VertexInputBindingDescription>();
|
||||
var vertexAttributeDescriptions =
|
||||
new VertexInputAttributeDescription[resources.VertexBuffers.Length];
|
||||
for (var index = 0; index < resources.VertexBuffers.Length; index++)
|
||||
{
|
||||
var vertexBuffer = resources.VertexBuffers[index];
|
||||
vertexBindingDescriptions[index] = new VertexInputBindingDescription
|
||||
var bufferKey = (vertexBuffer.Buffer.Handle, vertexBuffer.PerInstance);
|
||||
if (!bindingByBuffer.TryGetValue(bufferKey, out var bindingIndex))
|
||||
{
|
||||
Binding = (uint)index,
|
||||
Stride = vertexBuffer.Stride == 0
|
||||
? Math.Max(vertexBuffer.ComponentCount, 1) * sizeof(float)
|
||||
: vertexBuffer.Stride,
|
||||
InputRate = VertexInputRate.Vertex,
|
||||
};
|
||||
bindingIndex = (uint)vertexBindingList.Count;
|
||||
bindingByBuffer[bufferKey] = bindingIndex;
|
||||
vertexBindingList.Add(new VertexInputBindingDescription
|
||||
{
|
||||
Binding = bindingIndex,
|
||||
Stride = vertexBuffer.Stride == 0
|
||||
? Math.Max(vertexBuffer.ComponentCount, 1) * sizeof(float)
|
||||
: vertexBuffer.Stride,
|
||||
InputRate = vertexBuffer.PerInstance
|
||||
? VertexInputRate.Instance
|
||||
: VertexInputRate.Vertex,
|
||||
});
|
||||
}
|
||||
|
||||
vertexAttributeDescriptions[index] = new VertexInputAttributeDescription
|
||||
{
|
||||
Location = vertexBuffer.Location,
|
||||
Binding = (uint)index,
|
||||
Binding = bindingIndex,
|
||||
Format = ToVkVertexFormat(
|
||||
vertexBuffer.DataFormat,
|
||||
vertexBuffer.NumberFormat,
|
||||
vertexBuffer.ComponentCount),
|
||||
Offset = 0,
|
||||
Offset = vertexBuffer.OffsetBytes,
|
||||
};
|
||||
}
|
||||
|
||||
var vertexBindingDescriptions = vertexBindingList.ToArray();
|
||||
|
||||
fixed (VertexInputBindingDescription* vertexBindingPointerBase = vertexBindingDescriptions)
|
||||
fixed (VertexInputAttributeDescription* vertexAttributePointerBase = vertexAttributeDescriptions)
|
||||
{
|
||||
@@ -9280,6 +9295,7 @@ internal static unsafe class VulkanVideoPresenter
|
||||
NumberFormat = guestBuffer.NumberFormat,
|
||||
Stride = guestBuffer.Stride,
|
||||
OffsetBytes = guestBuffer.OffsetBytes,
|
||||
PerInstance = guestBuffer.PerInstance,
|
||||
};
|
||||
}
|
||||
|
||||
@@ -9297,6 +9313,7 @@ internal static unsafe class VulkanVideoPresenter
|
||||
NumberFormat = guestBuffer.NumberFormat,
|
||||
Stride = guestBuffer.Stride,
|
||||
OffsetBytes = guestBuffer.OffsetBytes,
|
||||
PerInstance = guestBuffer.PerInstance,
|
||||
};
|
||||
|
||||
private VkBuffer CreateHostBuffer(
|
||||
@@ -9398,21 +9415,28 @@ internal static unsafe class VulkanVideoPresenter
|
||||
private static Format ToVkVertexFormat(
|
||||
uint dataFormat,
|
||||
uint numberFormat,
|
||||
uint componentCount) =>
|
||||
(dataFormat, numberFormat) switch
|
||||
uint componentCount)
|
||||
{
|
||||
var format = (dataFormat, numberFormat) switch
|
||||
{
|
||||
(1, 0) => Format.R8Unorm,
|
||||
(1, 1) => Format.R8SNorm,
|
||||
(1, 2) => Format.R8Uscaled,
|
||||
(1, 3) => Format.R8Sscaled,
|
||||
(1, 4) => Format.R8Uint,
|
||||
(1, 5) => Format.R8Sint,
|
||||
(1, 9) => Format.R8Srgb,
|
||||
(2, 0) => Format.R16Unorm,
|
||||
(2, 1) => Format.R16SNorm,
|
||||
(2, 2) => Format.R16Uscaled,
|
||||
(2, 3) => Format.R16Sscaled,
|
||||
(2, 4) => Format.R16Uint,
|
||||
(2, 5) => Format.R16Sint,
|
||||
(2, 7) => Format.R16Sfloat,
|
||||
(3, 0) => Format.R8G8Unorm,
|
||||
(3, 1) => Format.R8G8SNorm,
|
||||
(3, 2) => Format.R8G8Uscaled,
|
||||
(3, 3) => Format.R8G8Sscaled,
|
||||
(3, 4) => Format.R8G8Uint,
|
||||
(3, 5) => Format.R8G8Sint,
|
||||
(3, 9) => Format.R8G8Srgb,
|
||||
@@ -9467,6 +9491,9 @@ internal static unsafe class VulkanVideoPresenter
|
||||
(14, 4) => Format.R32G32B32A32Uint,
|
||||
(14, 5) => Format.R32G32B32A32Sint,
|
||||
(14, 7) => Format.R32G32B32A32Sfloat,
|
||||
// Prospero VertexAttribFormat quirks also seen as buffer formats.
|
||||
(113, _) => Format.R32G32B32A32Sfloat,
|
||||
(121, _) => Format.R16G16Sfloat,
|
||||
(16, 0) => Format.B5G6R5UnormPack16,
|
||||
(17, 0) => Format.R5G5B5A1UnormPack16,
|
||||
(19, 0) => Format.R4G4B4A4UnormPack16,
|
||||
@@ -9474,6 +9501,38 @@ internal static unsafe class VulkanVideoPresenter
|
||||
_ => ToVkFloatVertexFormat(componentCount),
|
||||
};
|
||||
|
||||
return NarrowVkVertexFormat(format, componentCount);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Narrow a sharp's full VkFormat to the component count the VS fetch
|
||||
/// actually consumes.
|
||||
/// </summary>
|
||||
private static Format NarrowVkVertexFormat(Format format, uint usedComponents)
|
||||
{
|
||||
if (usedComponents == 0)
|
||||
{
|
||||
return format;
|
||||
}
|
||||
|
||||
return (format, usedComponents) switch
|
||||
{
|
||||
(Format.R32G32B32A32Sfloat, 1) => Format.R32Sfloat,
|
||||
(Format.R32G32B32A32Sfloat, 2) => Format.R32G32Sfloat,
|
||||
(Format.R32G32B32A32Sfloat, 3) => Format.R32G32B32Sfloat,
|
||||
(Format.R32G32B32Sfloat, 1) => Format.R32Sfloat,
|
||||
(Format.R32G32B32Sfloat, 2) => Format.R32G32Sfloat,
|
||||
(Format.R16G16B16A16Sfloat, 1) => Format.R16Sfloat,
|
||||
(Format.R16G16B16A16Sfloat, 2) => Format.R16G16Sfloat,
|
||||
(Format.R8G8B8A8Unorm, 1) => Format.R8Unorm,
|
||||
(Format.R8G8B8A8Unorm, 2) => Format.R8G8Unorm,
|
||||
(Format.R8G8B8A8SNorm, 2) => Format.R8G8SNorm,
|
||||
(Format.R8G8B8A8Uint, 1) => Format.R8Uint,
|
||||
(Format.R8G8B8A8Uint, 2) => Format.R8G8Uint,
|
||||
_ => format,
|
||||
};
|
||||
}
|
||||
|
||||
private static Format ToVkFloatVertexFormat(uint componentCount) =>
|
||||
componentCount switch
|
||||
{
|
||||
|
||||
@@ -312,7 +312,8 @@ public sealed record Gen5VertexInputBinding(
|
||||
uint OffsetBytes,
|
||||
byte[] Data,
|
||||
int DataLength,
|
||||
bool DataPooled);
|
||||
bool DataPooled,
|
||||
bool PerInstance = false);
|
||||
|
||||
public sealed record Gen5ShaderEvaluation(
|
||||
IReadOnlyList<uint> InitialScalarRegisters,
|
||||
|
||||
@@ -883,8 +883,11 @@ public static class Gen5ShaderScalarEvaluator
|
||||
Gen5ShaderInstruction instruction,
|
||||
Gen5BufferMemoryControl control,
|
||||
BufferDescriptor descriptor) =>
|
||||
// AGC embedded fetch is BufferLoadFormat/TBufferLoadFormat with idxen.
|
||||
// offen is allowed: the constant/scalar offset folds into OffsetBytes
|
||||
// (UI glyph shaders use this shape). Rejecting offen left those loads
|
||||
// as live SSBOs and dropped vertex attributes.
|
||||
control.IndexEnabled &&
|
||||
!control.OffsetEnabled &&
|
||||
control.DwordCount is >= 1 and <= 4 &&
|
||||
descriptor.BaseAddress != 0 &&
|
||||
descriptor.Stride != 0 &&
|
||||
|
||||
@@ -0,0 +1,293 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Buffers.Binary;
|
||||
using SharpEmu.HLE;
|
||||
using SharpEmu.Libs.Agc;
|
||||
using SharpEmu.ShaderCompiler;
|
||||
using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests.Agc;
|
||||
|
||||
/// <summary>
|
||||
/// Coverage for AGC attrib-table → BufferFormat merge and semantic indexing.
|
||||
/// </summary>
|
||||
public sealed class AgcVertexMetadataTests
|
||||
{
|
||||
[Fact]
|
||||
public void BuildVertexResources_UsesSemanticNotHardwareMappingAsAttribIndex()
|
||||
{
|
||||
// input_semantics[0]: semantic=1, hardware_mapping=4, size=2
|
||||
// If hardware_mapping were wrongly used as the attrib index, we'd read
|
||||
// attrib[4] instead of attrib[1] and get the wrong format/offset.
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
// ShaderSemantic word: semantic=1, hw_mapping=4, size_in_elements=2
|
||||
WriteUInt32(memory, semanticsAddress, 1u | (4u << 8) | (2u << 16));
|
||||
|
||||
// attrib[0] unused garbage
|
||||
WriteUInt32(memory, attribTable, 0xDEAD_BEEFu);
|
||||
// attrib[1]: buffer=0, format=k16_16Float(29), offset=8, fetch=0
|
||||
WriteUInt32(memory, attribTable + 4, 0u | (29u << 5) | (8u << 14));
|
||||
|
||||
// V# at buffer table[0]: base=sharpBase, stride=16
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(
|
||||
memory,
|
||||
bufferTable + 4,
|
||||
(uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[8] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[9] = (uint)(attribTable >> 32);
|
||||
scalars[10] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[11] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 10,
|
||||
VertexAttribReg: 8,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
Assert.True(
|
||||
AgcVertexMetadata.TryBuildVertexResourcesFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
out var resources));
|
||||
Assert.Single(resources);
|
||||
Assert.Equal(1u, resources[0].Semantic);
|
||||
Assert.Equal(4u, resources[0].HardwareMapping);
|
||||
Assert.Equal(8u, resources[0].OffsetBytes);
|
||||
Assert.Equal(5u, resources[0].DataFormat); // R16G16
|
||||
Assert.Equal(7u, resources[0].NumberFormat); // Float
|
||||
Assert.Equal(2u, resources[0].ComponentCount);
|
||||
Assert.Equal(sharpBase, resources[0].SharpBase);
|
||||
Assert.False(resources[0].PerInstance);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_OverlaysFormatWithoutRebasingCapture()
|
||||
{
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
// format k8_8_8_8UNorm(56), offset=12
|
||||
WriteUInt32(memory, attribTable, 0u | (56u << 5) | (12u << 14));
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
Pc: 0x40,
|
||||
Location: 0,
|
||||
ComponentCount: 4,
|
||||
DataFormat: 14, // wrong IR guess
|
||||
NumberFormat: 7,
|
||||
BaseAddress: sharpBase,
|
||||
Stride: 16,
|
||||
OffsetBytes: 0,
|
||||
Data: data,
|
||||
DataLength: data.Length,
|
||||
DataPooled: false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Single(merged);
|
||||
Assert.Equal(0u, merged[0].Location);
|
||||
Assert.Equal(sharpBase, merged[0].BaseAddress);
|
||||
Assert.Same(data, merged[0].Data);
|
||||
Assert.Equal(10u, merged[0].DataFormat); // RGBA8
|
||||
Assert.Equal(0u, merged[0].NumberFormat); // Unorm
|
||||
Assert.Equal(12u, merged[0].OffsetBytes);
|
||||
Assert.Equal(0x40u, merged[0].Pc);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_AcceptsVertexAttribFormatEnums()
|
||||
{
|
||||
// Attrib tables store VertexAttribFormat (227 = rgba8 unorm), not
|
||||
// BufferFormat (56). Without conversion the format patch is a no-op.
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, attribTable, 0u | (227u << 5) | (12u << 14)); // VertexAttribFormat
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
0x40, 0, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Equal(10u, merged[0].DataFormat);
|
||||
Assert.Equal(0u, merged[0].NumberFormat);
|
||||
Assert.Equal(12u, merged[0].OffsetBytes);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_MatchesInterleavedAttrsByOffsetNotBareBase()
|
||||
{
|
||||
// Both attributes share SharpBase. Matching by base alone would assign
|
||||
// the color format to position (video/UI regression).
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
// semantic0 → pos float4 @0; semantic1 → color rgba8 @12
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, semanticsAddress + 4, 1u | (4u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, attribTable, 0u | (77u << 5) | (0u << 14)); // k32_32_32_32Float
|
||||
WriteUInt32(memory, attribTable + 4, 0u | (56u << 5) | (12u << 14)); // rgba8unorm @12
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 2,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
0x40, 0, 4, 14, 7, sharpBase, 16, 0, data, data.Length, false),
|
||||
new Gen5VertexInputBinding(
|
||||
0x80, 1, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Equal(2, merged.Count);
|
||||
Assert.Equal(0u, merged[0].OffsetBytes);
|
||||
Assert.Equal(12u, merged[1].OffsetBytes);
|
||||
Assert.Equal(0u, merged[1].NumberFormat); // Unorm color, not float
|
||||
Assert.Equal(10u, merged[1].DataFormat); // RGBA8
|
||||
Assert.Equal(sharpBase, merged[0].BaseAddress);
|
||||
Assert.Equal(sharpBase, merged[1].BaseAddress);
|
||||
Assert.Same(data, merged[0].Data);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void CollectFetchPrologPcs_FindsSBufferLoadsFromTableRegisters()
|
||||
{
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 10,
|
||||
VertexAttribReg: 8,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: 1);
|
||||
|
||||
var program = new Gen5ShaderProgram(
|
||||
0,
|
||||
[
|
||||
new Gen5ShaderInstruction(
|
||||
0x10,
|
||||
Gen5ShaderEncoding.Smem,
|
||||
"SBufferLoadDword",
|
||||
Words: [],
|
||||
Sources: [Gen5Operand.Scalar(8)],
|
||||
Destinations: [Gen5Operand.Scalar(20)],
|
||||
new Gen5ScalarMemoryControl(1, 0, null)),
|
||||
new Gen5ShaderInstruction(
|
||||
0x20,
|
||||
Gen5ShaderEncoding.Smem,
|
||||
"SBufferLoadDword",
|
||||
Words: [],
|
||||
Sources: [Gen5Operand.Scalar(12)],
|
||||
Destinations: [Gen5Operand.Scalar(24)],
|
||||
new Gen5ScalarMemoryControl(1, 0, null)),
|
||||
new Gen5ShaderInstruction(
|
||||
0x30,
|
||||
Gen5ShaderEncoding.Sopp,
|
||||
"SEndpgm",
|
||||
Words: [],
|
||||
Sources: [],
|
||||
Destinations: [],
|
||||
null),
|
||||
]);
|
||||
|
||||
var pcs = AgcVertexMetadata.CollectFetchPrologPcs(program, tables);
|
||||
Assert.Contains(0x10u, pcs);
|
||||
Assert.DoesNotContain(0x20u, pcs);
|
||||
}
|
||||
|
||||
private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
|
||||
{
|
||||
Span<byte> bytes = stackalloc byte[4];
|
||||
BinaryPrimitives.WriteUInt32LittleEndian(bytes, value);
|
||||
Assert.True(memory.TryWrite(address, bytes));
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user