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https://github.com/par274/sharpemu.git
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AGC: correct GS program registers, stop dropping rect-list draws, add a missing size export (#734)
Three defects found while bringing up a PS5 title. None are title-specific. SPI_SHADER_PGM_LO_GS / HI_GS were 0x8A/0x8B, which are actually SPI_SHADER_PGM_RSRC1/RSRC2_GS. Reading them as an address produced a 58-bit value (observed live: 0x30004622C008300). The correct offsets are 0x88/0x89, consistent with SPI_SHADER_PGM_CHKSUM_GS = 0x80 and SPI_SHADER_PGM_LO_ES = 0xC8 already in the table. Draw translation dropped any RECT_LIST draw whose vertex program exported no parameters while the pixel shader had interpolated inputs. A disposition census over a real run measured this deleting ~620 of every 5000 draws (12%). Rect lists are what AMD drivers emit for clears, blits and resolves, so the guard was deleting clears and leaving previous frame contents on screen as trails. Rendering a draw whose interpolants are undefined is strictly better than deleting it. sceAgcDcbDrawIndexIndirectMultiGetSize was unimplemented while sceAgcDcbDrawIndexIndirectMulti emits an eight-dword packet. A title that sizes its command buffer from the missing export under-reserves by three dwords. NID derived with Ps5Nid.Compute, which reproduces the committed NIDs of the neighbouring exports. Tests: AgcContextRegisterTests and AgcShaderStageRegisterTests drive real PM4 packets through sceAgcDriverSubmitDcb and assert what the parser retained for the context and SH register dictionaries, via two new internal accessors; neither dictionary had any test surface, which is why register questions previously cost five-minute game runs.
This commit is contained in:
Arseny Yankovsky
@@ -95,8 +95,10 @@ public static partial class AgcExports
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private const uint SpiShaderPgmRsrc1Hs = 0x10A;
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private const uint SpiShaderPgmLoLs = 0x148;
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private const uint SpiShaderPgmHiLs = 0x149;
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private const uint SpiShaderPgmLoGs = 0x8A;
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private const uint SpiShaderPgmHiGs = 0x8B;
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// Not 0x8A/0x8B - those are SPI_SHADER_PGM_RSRC1/RSRC2_GS, and reading them
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// as an address yields a 58-bit value (observed live: 0x30004622C008300).
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private const uint SpiShaderPgmLoGs = 0x88;
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private const uint SpiShaderPgmHiGs = 0x89;
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private const uint SpiShaderPgmChksumGs = 0x80;
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private const uint SpiPsInputEna = 0x1B3;
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private const uint SpiPsInputAddr = 0x1B4;
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@@ -2174,6 +2176,18 @@ public static partial class AgcExports
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return (int)ctx[CpuRegister.Rax];
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}
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[SysAbiExport(
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Nid = "r98I08t+LOg",
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ExportName = "sceAgcDcbDrawIndexIndirectMultiGetSize",
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Target = Generation.Gen5,
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LibraryName = "libSceAgc")]
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public static int DcbDrawIndexIndirectMultiGetSize(CpuContext ctx)
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{
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// Eight, matching the packet DcbDrawIndexIndirectMulti emits.
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ctx[CpuRegister.Rax] = 8u * sizeof(uint);
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return (int)ctx[CpuRegister.Rax];
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}
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[SysAbiExport(
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Nid = "rUuVjyR+Rd4",
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ExportName = "sceAgcDcbGetLodStatsGetSize",
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@@ -6426,6 +6440,48 @@ public static partial class AgcExports
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}
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}
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/// <summary>
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/// Test-only view of a parsed graphics context register. False when the
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/// register was never written.
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/// </summary>
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internal static bool TryGetGraphicsContextRegisterForTests(
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CpuContext ctx,
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uint registerOffset,
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out uint value)
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{
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value = 0;
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if (!_submittedGpuStates.TryGetValue(ctx.Memory, out var gpuState))
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{
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return false;
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}
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lock (gpuState.Gate)
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{
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return gpuState.Graphics.CxRegisters.TryGetValue(registerOffset, out value);
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}
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}
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/// <summary>
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/// SH-register counterpart of <see cref="TryGetGraphicsContextRegisterForTests"/>;
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/// the shader stage addresses live here.
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/// </summary>
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internal static bool TryGetGraphicsShRegisterForTests(
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CpuContext ctx,
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uint registerOffset,
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out uint value)
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{
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value = 0;
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if (!_submittedGpuStates.TryGetValue(ctx.Memory, out var gpuState))
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{
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return false;
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}
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lock (gpuState.Gate)
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{
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return gpuState.Graphics.ShRegisters.TryGetValue(registerOffset, out value);
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}
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}
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/// <summary>
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/// GraphicsDcbSetIndexSize writes VGT_INDEX_TYPE via SET_UCONFIG_REG.
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/// Mirror that into <see cref="SubmittedDcbState.IndexSize"/>.
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@@ -7444,22 +7500,6 @@ public static partial class AgcExports
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}
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}
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state.UcRegisters.TryGetValue(VgtPrimitiveType, out var earlyPrimitiveType);
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if (IsRectListPrimitive(earlyPrimitiveType) &&
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(exportEvaluation.VertexInputs is null || exportEvaluation.VertexInputs.Count == 0) &&
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!VertexProgramExportsParameters(exportState.Program) &&
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GetInterpolatedAttributeCount(pixelState) != 0)
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{
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ReturnPooledEvaluationArrays(exportEvaluation);
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ReturnPooledEvaluationArrays(pixelEvaluation);
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error =
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$"rect-list-no-param-exports ps_inputs={GetInterpolatedAttributeCount(pixelState)}";
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TraceAgcShader(
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$"agc.rect_list_skip es=0x{exportShaderAddress:X16} " +
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$"ps=0x{pixelShaderAddress:X16} {error}");
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return false;
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}
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// Every bound color target the shader exports to. Deferred renderers
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// draw a multi-render-target G-buffer (up to eight slots) in one pass.
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// Fall back to slot 0 if we cannot match any export to a bound target.
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@@ -8236,20 +8276,6 @@ public static partial class AgcExports
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? (packedMasks >> (int)(target * 4)) & 0xFu
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: 0;
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private static bool VertexProgramExportsParameters(Gen5ShaderProgram program)
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{
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foreach (var instruction in program.Instructions)
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{
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if (instruction.Control is Gen5ExportControl export &&
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export.Target is >= 32 and < 64)
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{
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return true;
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}
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}
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return false;
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}
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private static uint GetInterpolatedAttributeCount(Gen5ShaderState state)
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{
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var maxAttribute = -1;
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@@ -12673,9 +12699,6 @@ public static partial class AgcExports
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private static bool IsEsGeometryShaderType(byte shaderType) =>
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shaderType is GsShaderType or GsBackShaderType;
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private static bool IsRectListPrimitive(uint primitiveType) =>
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AgcPrimitiveHelpers.IsRectListPrimitive(primitiveType);
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private static int SetIndirectPatchAddress(CpuContext ctx, string registerSpace)
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{
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var commandAddress = ctx[CpuRegister.Rdi];
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@@ -0,0 +1,215 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Agc;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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/// <summary>
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/// Coverage for the graphics context-register path in the PM4 parser. Draw
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/// translation reads render state out of this dictionary (CB_TARGET_MASK
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/// decides whether a draw writes alpha, CB_COLOR_CONTROL decides what the draw
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/// means), so a write that lands under the wrong key, or fails to overwrite an
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/// earlier one, silently changes what every later draw does. These drive real
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/// PM4 packets through the public submit export and assert what the parser
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/// retained.
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/// </summary>
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public sealed class AgcContextRegisterTests
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{
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private const ulong BaseAddress = 0x2_0000_0000;
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private const ulong SubmitPacketAddress = BaseAddress + 0x40;
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private const ulong CommandAddress = BaseAddress + 0x200;
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private const ulong IndirectTableAddress = BaseAddress + 0x600;
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private const uint ItNop = 0x10;
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private const uint ItSetContextReg = 0x69;
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private const uint RCxRegsIndirect = 0x12;
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private const uint CbTargetMask = 0x8E;
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private const uint CbColorControl = 0x202;
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// PM4 type-3 header: 0xC0000000 | ((dwords - 2) << 16) | (opcode << 8), with the
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// NOP sub-register in bits 2..7 — the parser reads it as (header >> 2) & 0x3F.
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private static uint Pm4Header(uint dwords, uint opcode, uint register = 0) =>
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0xC000_0000u | ((dwords - 2) << 16) | (opcode << 8) | ((register & 0x3Fu) << 2);
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[Fact]
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public void SetContextRegRetainsTargetMask()
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{
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var ctx = CreateContext(out var memory);
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WriteDwords(
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memory,
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CommandAddress,
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Pm4Header(3, ItSetContextReg),
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CbTargetMask,
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0x0000_0007u);
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Submit(ctx, memory, dwordCount: 3);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbTargetMask, out var value));
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Assert.Equal(0x0000_0007u, value);
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}
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/// <summary>
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/// The indirect form carries (offset, value) pairs out of guest memory
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/// rather than inline dwords, so an offset-encoding mismatch here would
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/// store the register under a key no reader looks at.
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/// </summary>
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[Fact]
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public void IndirectRegisterWriteRetainsTargetMask()
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{
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var ctx = CreateContext(out var memory);
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WriteIndirectRegisterCommand(memory, (CbTargetMask, 0xFFFF_FFFFu));
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Submit(ctx, memory, dwordCount: 4);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbTargetMask, out var value));
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Assert.Equal(0xFFFF_FFFFu, value);
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}
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/// <summary>
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/// Context registers persist across submissions on hardware until something
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/// clears them, so a mask written in one submission has to still be there
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/// for a draw in the next.
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/// </summary>
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[Fact]
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public void TargetMaskSurvivesASecondSubmission()
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{
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var ctx = CreateContext(out var memory);
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WriteIndirectRegisterCommand(memory, (CbTargetMask, 0x8888_8888u));
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Submit(ctx, memory, dwordCount: 4);
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// A second, unrelated submission: a bare NOP that touches no registers.
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WriteDwords(memory, CommandAddress, Pm4Header(2, ItNop), 0);
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Submit(ctx, memory, dwordCount: 2);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbTargetMask, out var value));
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Assert.Equal(0x8888_8888u, value);
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}
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/// <summary>
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/// Both encodings must land on the same key, or a title that sets the
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/// register one way and a reader that expects the other silently disagree.
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/// </summary>
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[Fact]
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public void DirectAndIndirectWritesShareOneKey()
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{
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var ctx = CreateContext(out var memory);
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WriteDwords(
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memory,
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CommandAddress,
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Pm4Header(3, ItSetContextReg),
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CbTargetMask,
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0x0000_0007u);
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Submit(ctx, memory, dwordCount: 3);
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WriteIndirectRegisterCommand(memory, (CbTargetMask, 0x0000_000Fu));
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Submit(ctx, memory, dwordCount: 4);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbTargetMask, out var value));
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Assert.Equal(0x0000_000Fu, value);
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}
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/// <summary>
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/// CB_COLOR_CONTROL (0x202) MODE bits [6:4] give Normal=1,
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/// EliminateFastClear=2, Resolve=3, FmaskDecompress=5, DccDecompress=6. The
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/// value has to survive the parser intact, ROP3 bits and all, because the
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/// mode decides whether a draw shades or resolves.
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/// </summary>
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[Theory]
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[InlineData(0x0000_0010u, 1u)] // Normal
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[InlineData(0x0000_0020u, 2u)] // EliminateFastClear
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[InlineData(0x00CC_0060u, 6u)] // DccDecompress, with ROP3=0xCC alongside
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public void ColorControlRetainsMode(uint written, uint expectedMode)
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{
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var ctx = CreateContext(out var memory);
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WriteIndirectRegisterCommand(memory, (CbColorControl, written));
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Submit(ctx, memory, dwordCount: 4);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbColorControl, out var value));
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Assert.Equal(written, value);
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Assert.Equal(expectedMode, (value >> 4) & 0x7u);
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}
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/// <summary>
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/// A later write must win. If the parser kept the first value, a draw that
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/// sets EliminateFastClear after an earlier Normal would still read Normal
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/// and the clear would be silently dropped.
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/// </summary>
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[Fact]
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public void ColorControlLaterWriteOverwritesEarlier()
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{
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var ctx = CreateContext(out var memory);
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WriteIndirectRegisterCommand(memory, (CbColorControl, 0x00CC_0010u));
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Submit(ctx, memory, dwordCount: 4);
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WriteIndirectRegisterCommand(memory, (CbColorControl, 0x00CC_0020u));
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Submit(ctx, memory, dwordCount: 4);
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Assert.True(
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AgcExports.TryGetGraphicsContextRegisterForTests(ctx, CbColorControl, out var value));
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Assert.Equal(0x00CC_0020u, value);
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Assert.Equal(2u, (value >> 4) & 0x7u);
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}
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private static void WriteIndirectRegisterCommand(
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FakeCpuMemory memory,
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params (uint Offset, uint Value)[] registers)
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{
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WriteDwords(
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memory,
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CommandAddress,
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Pm4Header(4, ItNop, RCxRegsIndirect),
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(uint)registers.Length,
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(uint)(IndirectTableAddress & 0xFFFF_FFFFu),
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(uint)(IndirectTableAddress >> 32));
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for (var index = 0; index < registers.Length; index++)
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{
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var entry = IndirectTableAddress + ((ulong)index * 8);
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WriteUInt32(memory, entry, registers[index].Offset);
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WriteUInt32(memory, entry + 4, registers[index].Value);
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}
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}
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private static void Submit(CpuContext ctx, FakeCpuMemory memory, uint dwordCount)
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{
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WriteUInt64(memory, SubmitPacketAddress, CommandAddress);
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WriteUInt32(memory, SubmitPacketAddress + 8, dwordCount);
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ctx[CpuRegister.Rdi] = SubmitPacketAddress;
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AgcExports.DriverSubmitDcb(ctx);
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}
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private static CpuContext CreateContext(out FakeCpuMemory memory)
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{
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memory = new FakeCpuMemory(BaseAddress, 0x1000);
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return new CpuContext(memory, Generation.Gen5);
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}
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private static void WriteDwords(FakeCpuMemory memory, ulong address, params uint[] values)
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{
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for (var index = 0; index < values.Length; index++)
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{
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WriteUInt32(memory, address + ((ulong)index * sizeof(uint)), values[index]);
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}
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}
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private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
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{
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Span<byte> buffer = stackalloc byte[sizeof(uint)];
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BinaryPrimitives.WriteUInt32LittleEndian(buffer, value);
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Assert.True(memory.TryWrite(address, buffer));
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}
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private static void WriteUInt64(FakeCpuMemory memory, ulong address, ulong value)
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{
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Span<byte> buffer = stackalloc byte[sizeof(ulong)];
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BinaryPrimitives.WriteUInt64LittleEndian(buffer, value);
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Assert.True(memory.TryWrite(address, buffer));
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}
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}
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@@ -0,0 +1,232 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Agc;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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/// <summary>
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/// Coverage for the SH-register path in the PM4 parser. A draw resolves its
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/// vertex stage from SPI_SHADER_PGM_LO_ES/HI_ES and its pixel stage from
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/// SPI_SHADER_PGM_LO_PS/HI_PS, both out of this dictionary, so a key that is
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/// dropped or written under a different encoding pairs a current pixel shader
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/// with a stale vertex shader — a failure that produces plausible-looking
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/// garbage rather than an error. These drive real PM4 packets through the
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/// public submit export and assert what the parser retained.
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/// </summary>
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public sealed class AgcShaderStageRegisterTests
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{
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private const ulong BaseAddress = 0x2_0000_0000;
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private const ulong SubmitPacketAddress = BaseAddress + 0x40;
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private const ulong CommandAddress = BaseAddress + 0x200;
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private const ulong IndirectTableAddress = BaseAddress + 0x600;
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private const uint ItNop = 0x10;
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private const uint ItSetShReg = 0x76;
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private const uint RShRegsIndirect = 0x11;
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// SH register offsets. ES is the vertex stage on GFX10 — the standalone
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// PGM_LO/HI_GS pair is dead post-GCN and the merged ES/GS stage is addressed
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// through ES.
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private const uint SpiShaderPgmLoPs = 0x8;
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private const uint SpiShaderPgmLoEs = 0xC8;
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private const uint SpiShaderPgmHiEs = 0xC9;
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private static uint Pm4Header(uint dwords, uint opcode, uint register = 0) =>
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0xC000_0000u | ((dwords - 2) << 16) | (opcode << 8) | ((register & 0x3Fu) << 2);
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/// <summary>
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/// The baseline: a direct SET_SH_REG write of the vertex stage address has
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/// to be readable afterwards. If this fails, nothing downstream can pair
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/// shaders correctly.
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/// </summary>
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[Fact]
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public void SetShRegRetainsExportShaderAddress()
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{
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var ctx = CreateContext(out var memory);
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WriteDwords(
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memory,
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CommandAddress,
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Pm4Header(3, ItSetShReg),
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SpiShaderPgmLoEs,
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0x0044_8582u);
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Submit(ctx, memory, dwordCount: 3);
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Assert.True(
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AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var value));
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Assert.Equal(0x0044_8582u, value);
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}
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/// <summary>
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/// The indirect encoding must land on the same keys as the direct one. A
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/// mismatch would store the stage address where the draw never reads it,
|
||||
/// leaving the draw to see whatever a previous submission left behind.
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/// </summary>
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[Fact]
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public void IndirectShRegisterWriteRetainsExportShaderAddress()
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{
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var ctx = CreateContext(out var memory);
|
||||
WriteIndirectShRegisterCommand(memory, (SpiShaderPgmLoEs, 0x0044_8DD1u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var value));
|
||||
Assert.Equal(0x0044_8DD1u, value);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Both stages written in one submission must both read back as written. If
|
||||
/// the vertex stage kept an older value while the pixel stage updated, every
|
||||
/// draw after it would be mis-paired.
|
||||
/// </summary>
|
||||
[Fact]
|
||||
public void BothStagesUpdateTogetherWithinOneSubmission()
|
||||
{
|
||||
var ctx = CreateContext(out var memory);
|
||||
WriteIndirectShRegisterCommand(
|
||||
memory,
|
||||
(SpiShaderPgmLoEs, 0x0080_2933u),
|
||||
(SpiShaderPgmLoPs, 0x0044_858Au));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
WriteIndirectShRegisterCommand(
|
||||
memory,
|
||||
(SpiShaderPgmLoEs, 0x0044_8581u),
|
||||
(SpiShaderPgmLoPs, 0x0044_8719u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var es));
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoPs, out var ps));
|
||||
Assert.Equal(0x0044_8581u, es);
|
||||
Assert.Equal(0x0044_8719u, ps);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Updating only the pixel stage must leave the vertex stage at its previous
|
||||
/// value rather than dropping the key, or the draw falls back to whatever
|
||||
/// default the resolver finds.
|
||||
/// </summary>
|
||||
[Fact]
|
||||
public void PixelStageUpdateLeavesExportStageIntact()
|
||||
{
|
||||
var ctx = CreateContext(out var memory);
|
||||
WriteIndirectShRegisterCommand(memory, (SpiShaderPgmLoEs, 0x0044_8582u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
WriteIndirectShRegisterCommand(memory, (SpiShaderPgmLoPs, 0x0044_858Au));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var es));
|
||||
Assert.Equal(0x0044_8582u, es);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Stage addresses are 64-bit: LO carries bits 39:8 and HI the top bits, and
|
||||
/// the draw combines them. A HI retained from an earlier shader while LO
|
||||
/// updates resolves to a splice of two different programs.
|
||||
/// </summary>
|
||||
[Fact]
|
||||
public void HighAndLowHalvesUpdateTogether()
|
||||
{
|
||||
var ctx = CreateContext(out var memory);
|
||||
WriteIndirectShRegisterCommand(
|
||||
memory,
|
||||
(SpiShaderPgmLoEs, 0x0080_2933u),
|
||||
(SpiShaderPgmHiEs, 0x0000_0008u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
WriteIndirectShRegisterCommand(
|
||||
memory,
|
||||
(SpiShaderPgmLoEs, 0x0044_8582u),
|
||||
(SpiShaderPgmHiEs, 0x0000_0004u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var lo));
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmHiEs, out var hi));
|
||||
Assert.Equal(0x0044_8582u, lo);
|
||||
Assert.Equal(0x0000_0004u, hi);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// SH registers persist across submissions on hardware. A stage address set
|
||||
/// in one submission must still be there for a draw in the next.
|
||||
/// </summary>
|
||||
[Fact]
|
||||
public void ExportShaderAddressSurvivesASecondSubmission()
|
||||
{
|
||||
var ctx = CreateContext(out var memory);
|
||||
WriteIndirectShRegisterCommand(memory, (SpiShaderPgmLoEs, 0x0044_8583u));
|
||||
Submit(ctx, memory, dwordCount: 4);
|
||||
|
||||
WriteDwords(memory, CommandAddress, Pm4Header(2, ItNop), 0);
|
||||
Submit(ctx, memory, dwordCount: 2);
|
||||
|
||||
Assert.True(
|
||||
AgcExports.TryGetGraphicsShRegisterForTests(ctx, SpiShaderPgmLoEs, out var value));
|
||||
Assert.Equal(0x0044_8583u, value);
|
||||
}
|
||||
|
||||
private static void WriteIndirectShRegisterCommand(
|
||||
FakeCpuMemory memory,
|
||||
params (uint Offset, uint Value)[] registers)
|
||||
{
|
||||
WriteDwords(
|
||||
memory,
|
||||
CommandAddress,
|
||||
Pm4Header(4, ItNop, RShRegsIndirect),
|
||||
(uint)registers.Length,
|
||||
(uint)(IndirectTableAddress & 0xFFFF_FFFFu),
|
||||
(uint)(IndirectTableAddress >> 32));
|
||||
|
||||
for (var index = 0; index < registers.Length; index++)
|
||||
{
|
||||
var entry = IndirectTableAddress + ((ulong)index * 8);
|
||||
WriteUInt32(memory, entry, registers[index].Offset);
|
||||
WriteUInt32(memory, entry + 4, registers[index].Value);
|
||||
}
|
||||
}
|
||||
|
||||
private static void Submit(CpuContext ctx, FakeCpuMemory memory, uint dwordCount)
|
||||
{
|
||||
WriteUInt64(memory, SubmitPacketAddress, CommandAddress);
|
||||
WriteUInt32(memory, SubmitPacketAddress + 8, dwordCount);
|
||||
ctx[CpuRegister.Rdi] = SubmitPacketAddress;
|
||||
AgcExports.DriverSubmitDcb(ctx);
|
||||
}
|
||||
|
||||
private static CpuContext CreateContext(out FakeCpuMemory memory)
|
||||
{
|
||||
memory = new FakeCpuMemory(BaseAddress, 0x1000);
|
||||
return new CpuContext(memory, Generation.Gen5);
|
||||
}
|
||||
|
||||
private static void WriteDwords(FakeCpuMemory memory, ulong address, params uint[] values)
|
||||
{
|
||||
for (var index = 0; index < values.Length; index++)
|
||||
{
|
||||
WriteUInt32(memory, address + ((ulong)index * sizeof(uint)), values[index]);
|
||||
}
|
||||
}
|
||||
|
||||
private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(uint)];
|
||||
BinaryPrimitives.WriteUInt32LittleEndian(buffer, value);
|
||||
Assert.True(memory.TryWrite(address, buffer));
|
||||
}
|
||||
|
||||
private static void WriteUInt64(FakeCpuMemory memory, ulong address, ulong value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(ulong)];
|
||||
BinaryPrimitives.WriteUInt64LittleEndian(buffer, value);
|
||||
Assert.True(memory.TryWrite(address, buffer));
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user