mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-31 06:59:45 +08:00
[shader] add cfg and dataflow tests
This commit is contained in:
ParantezTech
@@ -0,0 +1,90 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Collections.Generic;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Ir;
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using Xunit;
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namespace SharpEmu.ShaderCompiler.Tests;
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public sealed class Gen5ImplicitVccTests
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{
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private static Gen5ShaderInstruction Vopc(uint pc, string opcode = "VCmpEqU32") =>
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new(pc, Gen5ShaderEncoding.Vopc, opcode, [0u], [], [], null);
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private static Gen5ShaderInstruction Vop2(uint pc, string opcode) =>
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new(pc, Gen5ShaderEncoding.Vop2, opcode, [0u], [], [Gen5Operand.Vector(0)], null);
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private static Gen5ShaderInstruction Nop(uint pc) =>
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new(pc, Gen5ShaderEncoding.Sop1, "SNop", [0u], [], [], null);
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[Fact]
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public void VopcIsRecognisedAsAnImplicitVccWriter()
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{
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vopc(0)));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vopc(0, "VCmpLtF32")));
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}
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[Fact]
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public void Vop2CarryFormsAreRecognised()
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{
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VAddCoCiU32")));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VSubCoCiU32")));
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Assert.True(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VSubrevCoCiU32")));
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}
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[Fact]
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public void PlainVop2DoesNotWriteVcc()
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{
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Assert.False(Gen5ScalarSsa.WritesVccImplicitly(Vop2(0, "VAddF32")));
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Assert.False(Gen5ScalarSsa.WritesVccImplicitly(Nop(0)));
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}
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[Fact]
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public void VopcDefinesBothVccHalves()
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{
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List<Gen5ShaderInstruction> program = [Vopc(0), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var low = ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccLo);
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var high = ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccHi);
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Assert.Equal(IrReachingState.Single, low.State);
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Assert.Equal(0u, low.DefinitionPc);
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Assert.Equal(IrReachingState.Single, high.State);
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Assert.Equal(0u, high.DefinitionPc);
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}
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[Fact]
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public void WithoutTheImplicitWriteVccWouldLookUndefined()
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{
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// The regression this models: before implicit VCC was tracked the offset
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// register reported "none" and its stale value was used as a byte offset.
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List<Gen5ShaderInstruction> program = [Nop(0), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrReachingState.None, ssa.GetReachingDefinitionAt(4, Gen5ScalarSsa.VccLo).State);
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}
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[Fact]
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public void VccWrittenOnBothBranchesBecomesMultiple()
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{
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List<Gen5ShaderInstruction> program =
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[
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new(0, Gen5ShaderEncoding.Sopp, "SCbranchScc0", [2u], [], [], null),
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Vopc(4),
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new(8, Gen5ShaderEncoding.Sopp, "SBranch", [1u], [], [], null),
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Vopc(12),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(
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IrReachingState.Multiple,
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ssa.GetReachingDefinitionAt(16, Gen5ScalarSsa.VccLo).State);
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}
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}
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@@ -0,0 +1,142 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Collections.Generic;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Ir;
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using Xunit;
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namespace SharpEmu.ShaderCompiler.Tests;
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public sealed class Gen5ReachingDefinitionTests
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{
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private static Gen5ShaderInstruction Load(uint pc, uint destination) =>
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new(
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pc,
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Gen5ShaderEncoding.Smem,
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"SLoadDwordx4",
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[0u, 0u],
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[Gen5Operand.Scalar(0)],
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[Gen5Operand.Scalar(destination)],
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null);
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private static Gen5ShaderInstruction Nop(uint pc) =>
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new(pc, Gen5ShaderEncoding.Sop1, "SNop", [0u], [], [], null);
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private static Gen5ShaderInstruction Branch(uint pc, string opcode, short wordOffset) =>
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new(
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pc,
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Gen5ShaderEncoding.Sopp,
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opcode,
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[unchecked((uint)(ushort)wordOffset)],
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[],
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[],
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null);
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[Fact]
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public void SingleDefinitionIsTracked()
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{
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List<Gen5ShaderInstruction> program = [Load(0, 16), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var reaching = ssa.GetReachingDefinitionAt(4, 16);
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Assert.Equal(IrReachingState.Single, reaching.State);
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Assert.Equal(0u, reaching.DefinitionPc);
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}
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[Fact]
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public void TwoDefinitionsOnDifferentPathsBecomeMultiple()
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{
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// The case that produced garbage descriptors: the same register is
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// written on both sides of a branch and read after the join.
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List<Gen5ShaderInstruction> program =
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[
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Branch(0, "SCbranchScc0", 2),
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Load(4, 16),
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Branch(8, "SBranch", 1),
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Load(12, 16),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrReachingState.Multiple, ssa.GetReachingDefinitionAt(16, 16).State);
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}
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[Fact]
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public void DefinitionOnOnlyOnePathIsAlsoMultipleAtTheJoin()
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{
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List<Gen5ShaderInstruction> program =
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[
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Load(0, 16),
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Branch(4, "SCbranchScc0", 1),
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Load(8, 16),
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Nop(12),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrReachingState.Multiple, ssa.GetReachingDefinitionAt(12, 16).State);
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}
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[Fact]
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public void DefinitionBeforeTheBranchStaysSingle()
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{
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List<Gen5ShaderInstruction> program =
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[
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Load(0, 16),
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Branch(4, "SCbranchScc0", 1),
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Load(8, 16),
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Nop(12),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var reaching = ssa.GetReachingDefinitionAt(4, 16);
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Assert.Equal(IrReachingState.Single, reaching.State);
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Assert.Equal(0u, reaching.DefinitionPc);
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}
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[Fact]
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public void UserDataCountsAsADefinition()
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{
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List<Gen5ShaderInstruction> program = [Nop(0)];
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var ssa = Gen5ScalarSsa.Build(program, userData: [0x1111, 0x2222]);
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Assert.Equal(IrReachingState.Single, ssa.GetReachingDefinitionAt(0, 0).State);
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Assert.Equal(IrReachingState.None, ssa.GetReachingDefinitionAt(0, 64).State);
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}
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[Fact]
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public void UnwrittenRegisterHasNoDefinition()
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{
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List<Gen5ShaderInstruction> program = [Load(0, 16), Nop(4)];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrReachingState.None, ssa.GetReachingDefinitionAt(4, 32).State);
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}
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[Fact]
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public void ReachingDefinitionSeesLoadsThatConstantPropagationCannot()
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{
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// The whole point of the second analysis: SLoadDwordx4 has no compile-time
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// value, so constant propagation reports Unknown and never Merged. Reaching
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// definitions still proves the register has two possible writers.
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List<Gen5ShaderInstruction> program =
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[
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Branch(0, "SCbranchScc0", 2),
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Load(4, 16),
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Branch(8, "SBranch", 1),
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Load(12, 16),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrScalarState.Unknown, ssa.GetScalarAt(16, 16).State);
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Assert.Equal(IrReachingState.Multiple, ssa.GetReachingDefinitionAt(16, 16).State);
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}
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}
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@@ -0,0 +1,168 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Collections.Generic;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Ir;
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using Xunit;
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namespace SharpEmu.ShaderCompiler.Tests;
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public sealed class Gen5ScalarSsaTests
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{
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private static Gen5ShaderInstruction Mov(uint pc, uint destination, uint literal) =>
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new(
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pc,
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Gen5ShaderEncoding.Sop1,
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"SMov",
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[0u],
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[new Gen5Operand(Gen5OperandKind.LiteralConstant, literal)],
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[Gen5Operand.Scalar(destination)],
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null);
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private static Gen5ShaderInstruction Nop(uint pc) =>
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new(pc, Gen5ShaderEncoding.Sop1, "SNop", [0u], [], [], null);
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private static Gen5ShaderInstruction Branch(uint pc, string opcode, short wordOffset) =>
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new(
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pc,
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Gen5ShaderEncoding.Sopp,
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opcode,
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[unchecked((uint)(ushort)wordOffset)],
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[],
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[],
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null);
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[Fact]
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public void StraightLineMovResolvesToAConstant()
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{
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List<Gen5ShaderInstruction> program =
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[
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Mov(0, destination: 8, literal: 0x1234),
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Nop(4),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var value = ssa.GetScalarAt(4, 8);
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Assert.Equal(IrScalarState.Constant, value.State);
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Assert.Equal(0x1234u, value.Constant);
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}
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[Fact]
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public void UserDataSeedsTheEntryState()
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{
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List<Gen5ShaderInstruction> program = [Nop(0)];
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var ssa = Gen5ScalarSsa.Build(program, userData: [0x40F55240, 0x00000004]);
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Assert.Equal(IrScalarState.Constant, ssa.GetScalarAt(0, 0).State);
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Assert.Equal(0x40F55240u, ssa.GetScalarAt(0, 0).Constant);
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Assert.Equal(0x00000004u, ssa.GetScalarAt(0, 1).Constant);
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}
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[Fact]
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public void ConflictingValuesFromTwoPathsBecomeMerged()
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{
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// if (cc) s8 = 0xAAAA else s8 = 0xBBBB; use s8
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List<Gen5ShaderInstruction> program =
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[
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Branch(0, "SCbranchScc0", 2),
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Mov(4, destination: 8, literal: 0xAAAA),
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Branch(8, "SBranch", 1),
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Mov(12, destination: 8, literal: 0xBBBB),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.True(ssa.Graph.HasControlFlow);
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Assert.Equal(IrScalarState.Merged, ssa.GetScalarAt(16, 8).State);
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}
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[Fact]
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public void SameValueOnBothPathsStaysResolved()
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{
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List<Gen5ShaderInstruction> program =
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[
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Branch(0, "SCbranchScc0", 2),
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Mov(4, destination: 8, literal: 0xCAFE),
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Branch(8, "SBranch", 1),
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Mov(12, destination: 8, literal: 0xCAFE),
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Nop(16),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var value = ssa.GetScalarAt(16, 8);
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Assert.Equal(IrScalarState.Constant, value.State);
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Assert.Equal(0xCAFEu, value.Constant);
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}
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[Fact]
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public void RegisterWrittenOnOnlyOnePathIsMergedAtTheJoin()
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{
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List<Gen5ShaderInstruction> program =
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[
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Mov(0, destination: 8, literal: 0x1111),
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Branch(4, "SCbranchScc0", 1),
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Mov(8, destination: 8, literal: 0x2222),
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Nop(12),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.Equal(IrScalarState.Merged, ssa.GetScalarAt(12, 8).State);
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}
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[Fact]
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public void ValueBeforeTheBranchIsStillResolved()
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{
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List<Gen5ShaderInstruction> program =
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[
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Mov(0, destination: 8, literal: 0x1111),
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Branch(4, "SCbranchScc0", 1),
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Mov(8, destination: 8, literal: 0x2222),
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Nop(12),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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var value = ssa.GetScalarAt(4, 8);
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Assert.Equal(IrScalarState.Constant, value.State);
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Assert.Equal(0x1111u, value.Constant);
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}
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[Fact]
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public void MergeJoinIsReportedForDivergentBlocks()
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{
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List<Gen5ShaderInstruction> program =
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[
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Branch(0, "SCbranchScc0", 1),
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Mov(4, destination: 8, literal: 1),
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Nop(8),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.True(ssa.IsInsideDivergentMerge(8));
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Assert.False(ssa.IsInsideDivergentMerge(0));
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}
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[Fact]
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public void LoopDoesNotHangTheFixpoint()
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{
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List<Gen5ShaderInstruction> program =
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[
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Mov(0, destination: 8, literal: 1),
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Nop(4),
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Branch(8, "SCbranchScc1", -3),
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Nop(12),
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];
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var ssa = Gen5ScalarSsa.Build(program, userData: []);
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Assert.NotEmpty(ssa.Graph.LoopHeaders);
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Assert.Equal(IrScalarState.Constant, ssa.GetScalarAt(12, 8).State);
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}
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}
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@@ -0,0 +1,127 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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||||
// SPDX-License-Identifier: GPL-2.0-or-later
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||||
|
||||
using System.Collections.Generic;
|
||||
using SharpEmu.ShaderCompiler;
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||||
using SharpEmu.ShaderCompiler.Ir;
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||||
using Xunit;
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||||
|
||||
namespace SharpEmu.ShaderCompiler.Tests;
|
||||
|
||||
public sealed class IrControlFlowTests
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||||
{
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||||
private sealed class Resolver : IIrBranchResolver
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||||
{
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||||
public Dictionary<uint, (bool Conditional, uint Target)> Branches { get; } = [];
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||||
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public bool IsBranch(Gen5ShaderInstruction instruction) =>
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Branches.ContainsKey(instruction.Pc);
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public bool IsConditional(Gen5ShaderInstruction instruction) =>
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Branches.TryGetValue(instruction.Pc, out var branch) && branch.Conditional;
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public bool TryGetBranchTarget(Gen5ShaderInstruction instruction, out uint targetPc)
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||||
{
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if (Branches.TryGetValue(instruction.Pc, out var branch))
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||||
{
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targetPc = branch.Target;
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return true;
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}
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targetPc = 0;
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return false;
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}
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||||
}
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private static Gen5ShaderInstruction Instruction(uint pc) =>
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new(pc, Gen5ShaderEncoding.Sop1, "SMov", [], [], [], null);
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||||
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||||
private static List<Gen5ShaderInstruction> Straight(params uint[] pcs)
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{
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||||
var list = new List<Gen5ShaderInstruction>();
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||||
foreach (var pc in pcs)
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||||
{
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list.Add(Instruction(pc));
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}
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return list;
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||||
}
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||||
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||||
[Fact]
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||||
public void StraightLineCodeIsASingleBlock()
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{
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var instructions = Straight(0, 4, 8, 12);
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||||
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||||
var cfg = IrControlFlowGraph.Build(instructions, new Resolver());
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||||
|
||||
Assert.Single(cfg.Blocks);
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Assert.False(cfg.HasControlFlow);
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||||
Assert.Empty(cfg.LoopHeaders);
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||||
}
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||||
|
||||
[Fact]
|
||||
public void ConditionalBranchSplitsIntoThreeBlocks()
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||||
{
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||||
var instructions = Straight(0, 4, 8, 12, 16);
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||||
var resolver = new Resolver();
|
||||
resolver.Branches[4] = (Conditional: true, Target: 12);
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||||
|
||||
var cfg = IrControlFlowGraph.Build(instructions, resolver);
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||||
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||||
Assert.Equal(3, cfg.Blocks.Count);
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||||
Assert.True(cfg.HasControlFlow);
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||||
|
||||
var entry = cfg.BlockByStartPc[0];
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||||
var fallthrough = cfg.BlockByStartPc[8];
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||||
var target = cfg.BlockByStartPc[12];
|
||||
|
||||
Assert.Contains(target, cfg.Successors[entry]);
|
||||
Assert.Contains(fallthrough, cfg.Successors[entry]);
|
||||
Assert.Contains(entry, cfg.Predecessors[target]);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void UnconditionalBranchDoesNotFallThrough()
|
||||
{
|
||||
var instructions = Straight(0, 4, 8, 12);
|
||||
var resolver = new Resolver();
|
||||
resolver.Branches[4] = (Conditional: false, Target: 12);
|
||||
|
||||
var cfg = IrControlFlowGraph.Build(instructions, resolver);
|
||||
|
||||
var entry = cfg.BlockByStartPc[0];
|
||||
var skipped = cfg.BlockByStartPc[8];
|
||||
var target = cfg.BlockByStartPc[12];
|
||||
|
||||
Assert.Equal([target], cfg.Successors[entry]);
|
||||
Assert.DoesNotContain(skipped, cfg.Successors[entry]);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void BackwardBranchMarksALoopHeader()
|
||||
{
|
||||
var instructions = Straight(0, 4, 8, 12);
|
||||
var resolver = new Resolver();
|
||||
resolver.Branches[8] = (Conditional: true, Target: 4);
|
||||
|
||||
var cfg = IrControlFlowGraph.Build(instructions, resolver);
|
||||
|
||||
var header = cfg.BlockByStartPc[4];
|
||||
Assert.Contains(header, cfg.LoopHeaders);
|
||||
Assert.Contains(header, cfg.Successors[cfg.BlockByStartPc[4]]);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeBlockRecordsBothPredecessors()
|
||||
{
|
||||
var instructions = Straight(0, 4, 8, 12, 16, 20);
|
||||
var resolver = new Resolver();
|
||||
resolver.Branches[0] = (Conditional: true, Target: 12);
|
||||
resolver.Branches[8] = (Conditional: false, Target: 16);
|
||||
|
||||
var cfg = IrControlFlowGraph.Build(instructions, resolver);
|
||||
|
||||
var merge = cfg.BlockByStartPc[16];
|
||||
Assert.Equal(2, cfg.Predecessors[merge].Count);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user