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AGC: follow command-buffer branches across arena switches (#720)
Implement sceAgcCbBranch and walk INDIRECT_BUFFER so submissions that continue in a linked buffer keep their flip and end-of-frame labels.
This commit is contained in:
kuba
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Agc;
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using SharpEmu.Libs.Kernel;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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// The kernel event-queue registry is process-wide static state; serialize against
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// other suites that register graphics events.
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[CollectionDefinition(AgcCommandBufferChainCollection.Name, DisableParallelization = true)]
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public sealed class AgcCommandBufferChainCollection
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{
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public const string Name = "AgcCommandBufferChainState";
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}
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// A submission is one link of a chain, not always the whole command stream. When a
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// title's command arena fills mid-frame it continues in a fresh buffer, links the two
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// with an INDIRECT_BUFFER packet and submits only the first link, so a parser that
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// stops at the end of the submitted window silently drops the rest of that frame --
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// including its flip and the end-of-frame labels the guest waits on.
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[Collection(AgcCommandBufferChainCollection.Name)]
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public sealed class AgcCommandBufferChainTests
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{
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private const ulong BaseAddress = 0x1_0000_0000;
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private const int MemorySize = 0x4000;
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private const ulong HandleOutAddress = BaseAddress + 0x100;
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private const ulong EventsAddress = BaseAddress + 0x200;
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private const ulong OutCountAddress = BaseAddress + 0x300;
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private const ulong TimeoutAddress = BaseAddress + 0x400;
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private const ulong SubmitPacketAddress = BaseAddress + 0x500;
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private const ulong StackAddress = BaseAddress + 0x600;
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private const ulong CommandBufferAddress = BaseAddress + 0x800;
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private const ulong FirstLinkAddress = BaseAddress + 0x1000;
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private const ulong SecondLinkAddress = BaseAddress + 0x2000;
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private const ulong WaitLabelAddress = BaseAddress + 0x3000;
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// Graphics-queue completions land on ident 0, so its absence is how a suspended
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// queue is observed without standing up a GPU backend.
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private const ulong GraphicsCompletionIdent = 0;
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[Fact]
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public void SubmittedDcb_FollowsIndirectBufferIntoTheChainedBuffer()
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{
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var memory = new FakeCpuMemory(BaseAddress, MemorySize);
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var ctx = new CpuContext(memory, Generation.Gen5);
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var equeue = CreateEqueue(ctx, memory);
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try
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{
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RegisterGraphicsCompletion(equeue);
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// The chained buffer parks on a label that never reaches its reference,
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// so reaching it at all suspends the queue.
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var secondLinkDwords = WriteUnsatisfiedWait(ctx, memory, SecondLinkAddress);
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var firstLinkDwords = WriteChain(
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ctx,
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memory,
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FirstLinkAddress,
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SecondLinkAddress,
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secondLinkDwords);
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SubmitDcb(ctx, memory, FirstLinkAddress, firstLinkDwords);
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Assert.NotEqual(
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(int)OrbisGen2Result.ORBIS_GEN2_OK,
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WaitEqueue(ctx, memory, equeue));
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}
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finally
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{
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DeleteEqueue(ctx, equeue);
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}
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}
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// Titles emit a zeroed INDIRECT_BUFFER as padding for a branch they decided not to
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// take. Treating that as a redirect truncates the frame it appears in.
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[Fact]
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public void SubmittedDcb_KeepsParsingPastAnEmptyIndirectBuffer()
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{
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var memory = new FakeCpuMemory(BaseAddress, MemorySize);
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var ctx = new CpuContext(memory, Generation.Gen5);
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var equeue = CreateEqueue(ctx, memory);
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try
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{
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RegisterGraphicsCompletion(equeue);
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var paddingDwords = WriteChain(ctx, memory, FirstLinkAddress, target: 0, targetDwords: 0);
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var waitDwords = WriteUnsatisfiedWait(
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ctx,
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memory,
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FirstLinkAddress + (paddingDwords * sizeof(uint)));
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SubmitDcb(ctx, memory, FirstLinkAddress, paddingDwords + waitDwords);
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Assert.NotEqual(
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(int)OrbisGen2Result.ORBIS_GEN2_OK,
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WaitEqueue(ctx, memory, equeue));
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}
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finally
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{
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DeleteEqueue(ctx, equeue);
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}
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}
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// A chain whose target is never satisfied must not be mistaken for a completed
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// submission: without the redirect the empty first link completes immediately.
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[Fact]
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public void SubmittedDcb_WithoutAChain_CompletesImmediately()
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{
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var memory = new FakeCpuMemory(BaseAddress, MemorySize);
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var ctx = new CpuContext(memory, Generation.Gen5);
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var equeue = CreateEqueue(ctx, memory);
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try
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{
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RegisterGraphicsCompletion(equeue);
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var paddingDwords = WriteChain(ctx, memory, FirstLinkAddress, target: 0, targetDwords: 0);
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SubmitDcb(ctx, memory, FirstLinkAddress, paddingDwords);
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Assert.Equal(
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(int)OrbisGen2Result.ORBIS_GEN2_OK,
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WaitEqueue(ctx, memory, equeue));
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Assert.Equal(GraphicsCompletionIdent, ReadUInt64(memory, EventsAddress + 0x00));
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}
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finally
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{
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DeleteEqueue(ctx, equeue);
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}
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}
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private static void RegisterGraphicsCompletion(ulong equeue) =>
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Assert.True(KernelEventQueueCompatExports.RegisterEvent(
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equeue,
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GraphicsCompletionIdent,
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KernelEventQueueCompatExports.KernelEventFilterGraphics,
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userData: 0));
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private static uint WriteChain(
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CpuContext ctx,
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FakeCpuMemory memory,
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ulong linkAddress,
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ulong target,
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uint targetDwords)
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{
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PointCommandBufferAt(memory, linkAddress);
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ctx[CpuRegister.Rdi] = CommandBufferAddress;
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ctx[CpuRegister.Rsi] = target;
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ctx[CpuRegister.Rdx] = targetDwords;
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, AgcExports.DcbJump(ctx));
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Assert.Equal(linkAddress, ctx[CpuRegister.Rax]);
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return 4;
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}
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private static uint WriteUnsatisfiedWait(CpuContext ctx, FakeCpuMemory memory, ulong linkAddress)
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{
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PointCommandBufferAt(memory, linkAddress);
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WriteUInt32(memory, WaitLabelAddress, 0);
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ctx[CpuRegister.Rsp] = StackAddress;
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ctx[CpuRegister.Rdi] = CommandBufferAddress;
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ctx[CpuRegister.Rsi] = 0; // 32-bit compare
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ctx[CpuRegister.Rdx] = 3; // equal
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ctx[CpuRegister.Rcx] = 4; // memory space
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ctx[CpuRegister.R8] = 2;
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ctx[CpuRegister.R9] = WaitLabelAddress;
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WriteUInt64(memory, StackAddress + 8, 1); // reference the label never reaches
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WriteUInt64(memory, StackAddress + 16, 0xFFFF_FFFF); // mask
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WriteUInt32(memory, StackAddress + 24, 0x10); // poll interval
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, AgcExports.DcbWaitRegMem(ctx));
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return 7;
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}
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private static void PointCommandBufferAt(FakeCpuMemory memory, ulong linkAddress)
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{
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WriteUInt64(memory, CommandBufferAddress + 0x10, linkAddress);
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WriteUInt64(memory, CommandBufferAddress + 0x18, linkAddress + 0x400);
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}
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private static void SubmitDcb(
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CpuContext ctx,
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FakeCpuMemory memory,
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ulong commandAddress,
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uint dwordCount)
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{
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WriteUInt64(memory, SubmitPacketAddress, commandAddress);
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WriteUInt32(memory, SubmitPacketAddress + 8, dwordCount);
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ctx[CpuRegister.Rdi] = SubmitPacketAddress;
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, AgcExports.DriverSubmitDcb(ctx));
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}
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private static ulong CreateEqueue(CpuContext ctx, FakeCpuMemory memory)
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{
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ctx[CpuRegister.Rdi] = HandleOutAddress;
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Assert.Equal(
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(int)OrbisGen2Result.ORBIS_GEN2_OK,
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KernelEventQueueCompatExports.KernelCreateEqueue(ctx));
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return ReadUInt64(memory, HandleOutAddress);
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}
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private static void DeleteEqueue(CpuContext ctx, ulong equeue)
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{
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ctx[CpuRegister.Rdi] = equeue;
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_ = KernelEventQueueCompatExports.KernelDeleteEqueue(ctx);
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}
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private static int WaitEqueue(CpuContext ctx, FakeCpuMemory memory, ulong equeue)
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{
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WriteUInt64(memory, TimeoutAddress, 0);
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ctx[CpuRegister.Rdi] = equeue;
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ctx[CpuRegister.Rsi] = EventsAddress;
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ctx[CpuRegister.Rdx] = 4;
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ctx[CpuRegister.Rcx] = OutCountAddress;
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ctx[CpuRegister.R8] = TimeoutAddress;
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return KernelEventQueueCompatExports.KernelWaitEqueue(ctx);
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}
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private static ulong ReadUInt64(FakeCpuMemory memory, ulong address)
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{
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Span<byte> buffer = stackalloc byte[8];
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Assert.True(memory.TryRead(address, buffer));
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return BinaryPrimitives.ReadUInt64LittleEndian(buffer);
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}
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private static void WriteUInt64(FakeCpuMemory memory, ulong address, ulong value)
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{
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Span<byte> buffer = stackalloc byte[8];
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BinaryPrimitives.WriteUInt64LittleEndian(buffer, value);
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Assert.True(memory.TryWrite(address, buffer));
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}
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private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
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{
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Span<byte> buffer = stackalloc byte[4];
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BinaryPrimitives.WriteUInt32LittleEndian(buffer, value);
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Assert.True(memory.TryWrite(address, buffer));
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}
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}
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