mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-25 20:28:48 +08:00
feat: implement cosf, time, ctype tables, tracked heap access, IL2CPP lookup ABI paths (#542)
* fix: add Messenger CRT and AGC compatibility shims * fix: keep Messenger IL2CPP bootstrap on HLE shims * Fix Messenger compatibility ABI handling * Make IL2CPP ABI regression tests portable
This commit is contained in:
Kurt Himebauch
@@ -2168,25 +2168,18 @@ public sealed partial class DirectExecutionBackend
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}
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var symbolNameAddress = cpuContext[CpuRegister.Rdi];
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var outputAddress = cpuContext[CpuRegister.Rsi];
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if (!TryReadAsciiZ(symbolNameAddress, 512, out var symbolName) ||
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outputAddress == 0 ||
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!TryResolveIl2CppApiAddress(symbolName, out var resolvedAddress) ||
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!TryWriteUInt64Compat(outputAddress, resolvedAddress))
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!TryResolveIl2CppApiAddress(symbolName, out var resolvedAddress))
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{
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Console.Error.WriteLine(
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$"[LOADER][WARN] il2cpp_api_lookup_symbol failed: name='{symbolName}' out=0x{outputAddress:X16}");
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if (outputAddress != 0)
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{
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_ = TryWriteUInt64Compat(outputAddress, 0);
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}
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cpuContext[CpuRegister.Rax] = ulong.MaxValue;
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return OrbisGen2Result.ORBIS_GEN2_OK;
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$"[LOADER][WARN] il2cpp_api_lookup_symbol failed: name='{symbolName}'");
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// il2cpp_api_lookup_symbol is a normal one-argument pointer-returning
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// function. In particular, RSI is not an output pointer; the title's
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// caller leaves it live from an earlier call. Do not write through it.
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return Il2CppApiLookupAbi.SetResult(cpuContext, resolved: false, address: 0);
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}
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cpuContext[CpuRegister.Rax] = 0;
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return OrbisGen2Result.ORBIS_GEN2_OK;
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return Il2CppApiLookupAbi.SetResult(cpuContext, resolved: true, resolvedAddress);
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}
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private bool TryResolveIl2CppApiAddress(string symbolName, out ulong address)
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@@ -2196,8 +2189,23 @@ public sealed partial class DirectExecutionBackend
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return true;
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}
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return Aerolib.Instance.TryGetByExportName(symbolName, out var symbol) &&
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TryResolveRuntimeSymbolAddress(symbol.Nid, out address);
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if (Aerolib.Instance.TryGetByExportName(symbolName, out var symbol) &&
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TryResolveRuntimeSymbolAddress(symbol.Nid, out address))
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{
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return true;
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}
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// Unity's IL2CPP API table is populated through this resolver, then the
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// returned pointers are called directly by the title. Use the callable
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// zero-return stub for missing APIs rather than a non-callable sentinel.
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if (symbolName.StartsWith("il2cpp_", StringComparison.Ordinal) &&
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_unresolvedReturnStub != 0)
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{
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address = (ulong)_unresolvedReturnStub;
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return true;
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}
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return false;
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}
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private OrbisGen2Result DispatchBootstrapBridge()
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@@ -0,0 +1,18 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using SharpEmu.Core.Cpu;
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using SharpEmu.HLE;
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namespace SharpEmu.Core.Cpu.Native;
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internal static class Il2CppApiLookupAbi
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{
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internal static OrbisGen2Result SetResult(CpuContext context, bool resolved, ulong address)
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{
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// il2cpp_api_lookup_symbol is a normal pointer-returning function:
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// the result is in RAX and RSI remains caller-owned state.
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context[CpuRegister.Rax] = resolved ? address : 0;
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return OrbisGen2Result.ORBIS_GEN2_OK;
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}
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}
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@@ -2965,6 +2965,38 @@ public static partial class AgcExports
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$"arg1=0x{ctx[CpuRegister.Rsi]:X16} arg2=0x{ctx[CpuRegister.Rdx]:X16}");
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return ReturnPointer(ctx, commandAddress);
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}
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// Synthetic labels for uncatalogued AGC helper NIDs; the NID is authoritative.
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#pragma warning disable SHEM006
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[SysAbiExport(
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Nid = "zlqfTyrQSPk",
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ExportName = "sceAgcUnknownZlqfTyrQSPk",
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Target = Generation.Gen5,
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LibraryName = "libSceAgc")]
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public static int UnknownZlqfTyrQSPk(CpuContext ctx)
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{
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TraceAgc(
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$"agc.unknown_zlqf rdi=0x{ctx[CpuRegister.Rdi]:X16} " +
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$"rsi=0x{ctx[CpuRegister.Rsi]:X16} rdx=0x{ctx[CpuRegister.Rdx]:X16} " +
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$"rcx=0x{ctx[CpuRegister.Rcx]:X16} r8=0x{ctx[CpuRegister.R8]:X16} r9=0x{ctx[CpuRegister.R9]:X16}");
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "dZGYu5wObJs",
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ExportName = "sceAgcUnknownDZGYu5wObJs",
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Target = Generation.Gen5,
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LibraryName = "libSceAgc")]
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public static int UnknownDZGYu5wObJs(CpuContext ctx)
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{
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TraceAgc(
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$"agc.unknown_dzgy rdi=0x{ctx[CpuRegister.Rdi]:X16} " +
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$"rsi=0x{ctx[CpuRegister.Rsi]:X16} rdx=0x{ctx[CpuRegister.Rdx]:X16} " +
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$"rcx=0x{ctx[CpuRegister.Rcx]:X16} r8=0x{ctx[CpuRegister.R8]:X16} r9=0x{ctx[CpuRegister.R9]:X16}");
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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#pragma warning restore SHEM006
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private static void EnqueueSubmittedDcb(
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@@ -21,6 +21,11 @@ public static class CxaGuardExports
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}
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private static readonly ConcurrentDictionary<ulong, GuardState> _inProgress = new();
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private static readonly ConcurrentDictionary<ulong, object> _onceGates = new();
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private const int OnceUninitialized = 0;
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private const int OnceInProgress = 1;
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private const int OnceComplete = 2;
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[SysAbiExport(
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Nid = "3GPpjQdAMTw",
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@@ -171,6 +176,167 @@ public static class CxaGuardExports
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "DiGVep5yB5w",
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ExportName = "_ZSt13_Execute_onceRSt9once_flagPFiPvS1_PS1_ES1_",
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Target = Generation.Gen4 | Generation.Gen5,
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LibraryName = "libc")]
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public static int ExecuteOnce(CpuContext ctx)
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{
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var onceAddress = ctx[CpuRegister.Rdi];
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var callbackAddress = ctx[CpuRegister.Rsi];
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var parameter = ctx[CpuRegister.Rdx];
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if (onceAddress == 0 || callbackAddress == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
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}
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if (!ctx.TryReadInt32(onceAddress, out var onceValue))
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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if (onceValue == OnceComplete)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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var gate = _onceGates.GetOrAdd(onceAddress, static _ => new object());
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lock (gate)
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{
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if (!ctx.TryReadInt32(onceAddress, out onceValue))
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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while (onceValue == OnceInProgress)
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{
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Monitor.Wait(gate, TimeSpan.FromMilliseconds(1));
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if (!ctx.TryReadInt32(onceAddress, out onceValue))
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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}
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if (onceValue == OnceComplete)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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if (!ctx.TryWriteInt32(onceAddress, OnceInProgress))
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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}
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var scheduler = GuestThreadExecution.Scheduler;
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var callbackSucceeded = false;
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string? callbackError = null;
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var allocator = ctx.Memory as IGuestMemoryAllocator;
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var hasScratchContext = false;
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ulong scratchContextAddress = 0;
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try
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{
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if (allocator is not null && allocator.TryAllocateGuestMemory(0x10, 0x10, out scratchContextAddress))
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{
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hasScratchContext = true;
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_ = ctx.TryWriteUInt64(scratchContextAddress, 0);
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_ = ctx.TryWriteUInt64(scratchContextAddress + 8, 0);
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}
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if (scheduler is null)
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{
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callbackError = "guest scheduler unavailable";
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}
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else if (scheduler.TryCallGuestFunction(
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ctx,
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callbackAddress,
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onceAddress,
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parameter,
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scratchContextAddress,
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0,
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0,
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"std::_Execute_once",
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out var returnValue,
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out callbackError))
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{
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callbackSucceeded = returnValue != 0;
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}
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}
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finally
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{
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if (hasScratchContext && allocator is not null)
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{
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_ = allocator.TryFreeGuestMemory(scratchContextAddress);
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}
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}
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lock (gate)
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{
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if (!callbackSucceeded)
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{
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_ = ctx.TryWriteInt32(onceAddress, OnceUninitialized);
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Monitor.PulseAll(gate);
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if (!string.IsNullOrWhiteSpace(callbackError))
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{
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Console.Error.WriteLine(
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$"[LOADER][WARN] std::_Execute_once callback failed: {callbackError}");
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}
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ctx[CpuRegister.Rax] = unchecked((ulong)(int)OrbisGen2Result.ORBIS_GEN2_ERROR_TRY_AGAIN);
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_TRY_AGAIN;
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}
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if (!ctx.TryWriteInt32(onceAddress, OnceComplete))
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{
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_ = ctx.TryWriteInt32(onceAddress, OnceUninitialized);
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Monitor.PulseAll(gate);
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ctx[CpuRegister.Rax] = unchecked((ulong)(int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT);
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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Monitor.PulseAll(gate);
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// A completed once flag no longer needs a host-side gate. Waiters
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// already holding this gate will observe OnceComplete after the
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// pulse; future callers take the fast path before looking it up.
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_ = _onceGates.TryRemove(onceAddress, out _);
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}
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "PsrRUg671K0",
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ExportName = "__cxa_increment_exception_refcount",
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Target = Generation.Gen4 | Generation.Gen5,
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LibraryName = "libc")]
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public static int CxaIncrementExceptionRefcount(CpuContext ctx)
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{
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_ = ctx[CpuRegister.Rdi];
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "MQFPAqQPt1s",
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ExportName = "__cxa_decrement_exception_refcount",
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Target = Generation.Gen4 | Generation.Gen5,
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LibraryName = "libc")]
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public static int CxaDecrementExceptionRefcount(CpuContext ctx)
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{
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_ = ctx[CpuRegister.Rdi];
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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private static bool TryReadGuardState(CpuContext ctx, ulong guardPtr, out ulong word, out bool initialized, out bool inProgress)
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{
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word = 0;
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@@ -5855,7 +5855,7 @@ public static partial class KernelMemoryCompatExports
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return true;
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}
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if (!TryReadHostMemory(address, destination))
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if (!TryReadTrackedLibcHeap(address, destination) && !TryReadHostMemory(address, destination))
|
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{
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return false;
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}
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@@ -5921,7 +5921,7 @@ public static partial class KernelMemoryCompatExports
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return true;
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}
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if (!TryWriteHostMemory(address, source))
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if (!TryWriteTrackedLibcHeap(address, source) && !TryWriteHostMemory(address, source))
|
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{
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return false;
|
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}
|
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@@ -6663,7 +6663,7 @@ public static partial class KernelMemoryCompatExports
|
||||
}
|
||||
}
|
||||
|
||||
internal static bool TryReadTrackedLibcHeap(
|
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internal static unsafe bool TryReadTrackedLibcHeap(
|
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ulong address,
|
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Span<byte> destination)
|
||||
{
|
||||
@@ -6687,7 +6687,54 @@ public static partial class KernelMemoryCompatExports
|
||||
continue;
|
||||
}
|
||||
|
||||
return TryReadHostMemory(address, destination);
|
||||
try
|
||||
{
|
||||
// Marshal.AllocHGlobal allocations are not present in the
|
||||
// emulator's POSIX HostMemory map, so TryReadHostMemory
|
||||
// would reject this already-bounds-checked range.
|
||||
new ReadOnlySpan<byte>((void*)address, destination.Length).CopyTo(destination);
|
||||
return true;
|
||||
}
|
||||
catch
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
private static unsafe bool TryWriteTrackedLibcHeap(ulong address, ReadOnlySpan<byte> source)
|
||||
{
|
||||
if (source.IsEmpty)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
var length = (ulong)source.Length;
|
||||
lock (_libcAllocGate)
|
||||
{
|
||||
foreach (var (allocationAddress, allocation) in _libcAllocations)
|
||||
{
|
||||
var allocationSize = (ulong)allocation.Size;
|
||||
var offset = address >= allocationAddress
|
||||
? address - allocationAddress
|
||||
: ulong.MaxValue;
|
||||
if (offset > allocationSize || length > allocationSize - offset)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
try
|
||||
{
|
||||
source.CopyTo(new Span<byte>((void*)address, source.Length));
|
||||
return true;
|
||||
}
|
||||
catch
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -45,7 +45,11 @@ public static class LibcStdioExports
|
||||
private const ushort CtypeBlank = 0x400; // _XB ' ' and '\t'
|
||||
|
||||
private static readonly object _ctypeTableGate = new();
|
||||
private static readonly object _ctypeLowerTableGate = new();
|
||||
private static readonly object _ctypeUpperTableGate = new();
|
||||
private static nint _ctypeTableBase;
|
||||
private static nint _ctypeLowerTableBase;
|
||||
private static nint _ctypeUpperTableBase;
|
||||
|
||||
[SysAbiExport(
|
||||
Nid = "xeYO4u7uyJ0",
|
||||
@@ -716,6 +720,28 @@ public static class LibcStdioExports
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(
|
||||
Nid = "1uJgoVq3bQU",
|
||||
ExportName = "_Getptolower",
|
||||
Target = Generation.Gen4 | Generation.Gen5,
|
||||
LibraryName = "libc")]
|
||||
public static int GetPtolower(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = unchecked((ulong)EnsureCtypeLowerTable());
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(
|
||||
Nid = "rcQCUr0EaRU",
|
||||
ExportName = "_Getptoupper",
|
||||
Target = Generation.Gen4 | Generation.Gen5,
|
||||
LibraryName = "libc")]
|
||||
public static int GetPtoupper(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = unchecked((ulong)EnsureCtypeUpperTable());
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
private static unsafe nint EnsureCtypeTable()
|
||||
{
|
||||
lock (_ctypeTableGate)
|
||||
@@ -740,6 +766,58 @@ public static class LibcStdioExports
|
||||
}
|
||||
}
|
||||
|
||||
private static unsafe nint EnsureCtypeLowerTable()
|
||||
{
|
||||
lock (_ctypeLowerTableGate)
|
||||
{
|
||||
if (_ctypeLowerTableBase != 0)
|
||||
{
|
||||
return _ctypeLowerTableBase;
|
||||
}
|
||||
|
||||
var storage = Marshal.AllocHGlobal(CtypeTableEntryCount * sizeof(ushort));
|
||||
var entries = new Span<ushort>((void*)storage, CtypeTableEntryCount);
|
||||
for (var i = 0; i < CtypeTableEntryCount; i++)
|
||||
{
|
||||
var c = i + CtypeTableLowerBound;
|
||||
entries[i] = c == -1
|
||||
? ushort.MaxValue
|
||||
: c is >= 0 and <= 0x7F
|
||||
? (ushort)char.ToLowerInvariant((char)c)
|
||||
: (ushort)(c & 0xFF);
|
||||
}
|
||||
|
||||
_ctypeLowerTableBase = storage - (CtypeTableLowerBound * sizeof(ushort));
|
||||
return _ctypeLowerTableBase;
|
||||
}
|
||||
}
|
||||
|
||||
private static unsafe nint EnsureCtypeUpperTable()
|
||||
{
|
||||
lock (_ctypeUpperTableGate)
|
||||
{
|
||||
if (_ctypeUpperTableBase != 0)
|
||||
{
|
||||
return _ctypeUpperTableBase;
|
||||
}
|
||||
|
||||
var storage = Marshal.AllocHGlobal(CtypeTableEntryCount * sizeof(ushort));
|
||||
var entries = new Span<ushort>((void*)storage, CtypeTableEntryCount);
|
||||
for (var i = 0; i < CtypeTableEntryCount; i++)
|
||||
{
|
||||
var c = i + CtypeTableLowerBound;
|
||||
entries[i] = c == -1
|
||||
? ushort.MaxValue
|
||||
: c is >= 0 and <= 0x7F
|
||||
? (ushort)char.ToUpperInvariant((char)c)
|
||||
: (ushort)(c & 0xFF);
|
||||
}
|
||||
|
||||
_ctypeUpperTableBase = storage - (CtypeTableLowerBound * sizeof(ushort));
|
||||
return _ctypeUpperTableBase;
|
||||
}
|
||||
}
|
||||
|
||||
private static ushort ComputeCtypeFlags(int c)
|
||||
{
|
||||
var isUpper = c is >= 'A' and <= 'Z';
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System;
|
||||
using SharpEmu.HLE;
|
||||
|
||||
namespace SharpEmu.Libs.Messenger;
|
||||
|
||||
/// <summary>Small Unity/libc compatibility shims exercised by The Messenger.</summary>
|
||||
public static class MessengerCompatExports
|
||||
{
|
||||
[SysAbiExport(Nid = "wLlFkwG9UcQ", ExportName = "time", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libc")]
|
||||
public static int Time(CpuContext ctx)
|
||||
{
|
||||
var seconds = DateTimeOffset.UtcNow.ToUnixTimeSeconds();
|
||||
var output = ctx[CpuRegister.Rdi];
|
||||
if (output != 0 && !ctx.TryWriteUInt64(output, unchecked((ulong)seconds)))
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
||||
}
|
||||
|
||||
ctx[CpuRegister.Rax] = unchecked((ulong)seconds);
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "M4YYbSFfJ8g", ExportName = "setenv", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libc")]
|
||||
public static int Setenv(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "-P6FNMzk2Kc", ExportName = "cosf", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libc")]
|
||||
public static int Cosf(CpuContext ctx)
|
||||
{
|
||||
// AMD64 passes a scalar float in XMM0 and returns it in XMM0. RDI is
|
||||
// unrelated caller state and must not be interpreted as the argument.
|
||||
ctx.GetXmmRegister(0, out var low, out var high);
|
||||
var value = BitConverter.Int32BitsToSingle(unchecked((int)low));
|
||||
var resultBits = unchecked((uint)BitConverter.SingleToInt32Bits(MathF.Cos(value)));
|
||||
ctx.SetXmmRegister(0, (low & 0xFFFFFFFF00000000UL) | resultBits, high);
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "YQ0navp+YIc", ExportName = "puts", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libc")]
|
||||
public static int Puts(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "KuOuD58hqn4", ExportName = "malloc_stats_fast", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libc")]
|
||||
public static int MallocStatsFast(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "-pnj3-7a6QA", ExportName = "unity_mono_set_user_malloc_mutex", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libunity")]
|
||||
public static int UnityMonoSetMallocMutex(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
[SysAbiExport(Nid = "35NoyMOtYpE", ExportName = "SetDataFolder", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libunity")]
|
||||
public static int SetDataFolder(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
|
||||
#pragma warning disable SHEM006
|
||||
[SysAbiExport(Nid = "cJ2Y4E-t258", ExportName = "il2cpp_api_register_symbol", Target = Generation.Gen4 | Generation.Gen5, LibraryName = "libil2cpp")]
|
||||
public static int Il2CppRegisterSymbol(CpuContext ctx)
|
||||
{
|
||||
ctx[CpuRegister.Rax] = 0;
|
||||
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
||||
}
|
||||
}
|
||||
#pragma warning restore SHEM006
|
||||
@@ -0,0 +1,119 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Runtime.InteropServices;
|
||||
using SharpEmu.Core.Cpu.Native;
|
||||
using SharpEmu.HLE;
|
||||
using SharpEmu.Libs.Kernel;
|
||||
using SharpEmu.Libs.LibcStdio;
|
||||
using SharpEmu.Libs.Messenger;
|
||||
using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests;
|
||||
|
||||
public sealed class MessengerCompatExportsTests
|
||||
{
|
||||
[Fact]
|
||||
public void Cosf_UsesScalarXmmArgumentAndReturn()
|
||||
{
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var context = new CpuContext(new FakeCpuMemory(memoryBase, 0x1000), Generation.Gen5);
|
||||
var input = 0.5f;
|
||||
var inputBits = unchecked((uint)BitConverter.SingleToInt32Bits(input));
|
||||
context[CpuRegister.Rdi] = 0xDEAD_BEEF; // Must not be used as the argument.
|
||||
context.SetXmmRegister(0, 0xAABB_CCDD_0000_0000UL | inputBits, 0x1122_3344_5566_7788UL);
|
||||
|
||||
Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, MessengerCompatExports.Cosf(context));
|
||||
|
||||
context.GetXmmRegister(0, out var low, out var high);
|
||||
var expectedBits = unchecked((uint)BitConverter.SingleToInt32Bits(MathF.Cos(input)));
|
||||
Assert.Equal(expectedBits, unchecked((uint)low));
|
||||
Assert.Equal(0xAABB_CCDDUL, low >> 32);
|
||||
Assert.Equal(0x1122_3344_5566_7788UL, high);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void CtypeCaseTables_MapAsciiCharacters()
|
||||
{
|
||||
var context = new CpuContext(new FakeCpuMemory(0x1_0000_0000, 0x1000), Generation.Gen5);
|
||||
|
||||
Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, LibcStdioExports.GetPtolower(context));
|
||||
var lower = unchecked((nint)(long)context[CpuRegister.Rax]);
|
||||
Assert.Equal((short)'a', Marshal.ReadInt16(lower + ('A' * sizeof(short))));
|
||||
Assert.Equal((short)'z', Marshal.ReadInt16(lower + ('z' * sizeof(short))));
|
||||
Assert.Equal((short)-1, Marshal.ReadInt16(lower - sizeof(short)));
|
||||
|
||||
Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, LibcStdioExports.GetPtoupper(context));
|
||||
var upper = unchecked((nint)(long)context[CpuRegister.Rax]);
|
||||
Assert.Equal((short)'A', Marshal.ReadInt16(upper + ('a' * sizeof(short))));
|
||||
Assert.Equal((short)'Z', Marshal.ReadInt16(upper + ('Z' * sizeof(short))));
|
||||
Assert.Equal((short)-1, Marshal.ReadInt16(upper - sizeof(short)));
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void Il2CppLookup_ReturnsPointerInRaxWithoutWritingRsi()
|
||||
{
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
const ulong nameAddress = memoryBase + 0x100;
|
||||
const ulong outputAddress = memoryBase + 0x200;
|
||||
const ulong resolvedAddress = 0x2_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x1000);
|
||||
memory.WriteCString(nameAddress, "il2cpp_test");
|
||||
var context = new CpuContext(memory, Generation.Gen5);
|
||||
context[CpuRegister.Rdi] = nameAddress;
|
||||
context[CpuRegister.Rsi] = outputAddress; // Live caller state, not an output pointer.
|
||||
Assert.True(context.TryWriteUInt64(outputAddress, 0xCAFE_BABE));
|
||||
|
||||
var result = Il2CppApiLookupAbi.SetResult(context, resolved: true, resolvedAddress);
|
||||
|
||||
Assert.Equal(OrbisGen2Result.ORBIS_GEN2_OK, result);
|
||||
Assert.Equal(resolvedAddress, context[CpuRegister.Rax]);
|
||||
Assert.True(context.TryReadUInt64(outputAddress, out var output));
|
||||
Assert.Equal(0xCAFE_BABEUL, output);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void Il2CppLookup_MissingApiReturnsNullWithoutWritingRsi()
|
||||
{
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
const ulong nameAddress = memoryBase + 0x100;
|
||||
const ulong outputAddress = memoryBase + 0x200;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x1000);
|
||||
memory.WriteCString(nameAddress, "il2cpp_missing");
|
||||
var context = new CpuContext(memory, Generation.Gen5);
|
||||
context[CpuRegister.Rdi] = nameAddress;
|
||||
context[CpuRegister.Rsi] = outputAddress;
|
||||
Assert.True(context.TryWriteUInt64(outputAddress, 0xCAFE_BABE));
|
||||
|
||||
var result = Il2CppApiLookupAbi.SetResult(context, resolved: false, address: 0);
|
||||
|
||||
Assert.Equal(OrbisGen2Result.ORBIS_GEN2_OK, result);
|
||||
Assert.Equal(0UL, context[CpuRegister.Rax]);
|
||||
Assert.True(context.TryReadUInt64(outputAddress, out var output));
|
||||
Assert.Equal(0xCAFE_BABEUL, output);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void TrackedLibcHeapFallback_ReadsAndWritesHostAllocation()
|
||||
{
|
||||
var context = new CpuContext(new FakeCpuMemory(0x1_0000_0000, 0x1000), Generation.Gen5);
|
||||
context[CpuRegister.Rdi] = 16;
|
||||
Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, KernelMemoryCompatExports.Malloc(context));
|
||||
var address = context[CpuRegister.Rax];
|
||||
Assert.NotEqual(0UL, address);
|
||||
|
||||
try
|
||||
{
|
||||
Assert.True(KernelMemoryCompatExports.TryWriteUInt64Compat(context, address, 0x1234_5678_9ABC_DEF0UL));
|
||||
Span<byte> bytes = stackalloc byte[8];
|
||||
Assert.True(KernelMemoryCompatExports.TryReadTrackedLibcHeap(address, bytes));
|
||||
Assert.True(KernelMemoryCompatExports.TryReadUInt64Compat(context, address, out var value));
|
||||
Assert.Equal(0x1234_5678_9ABC_DEF0UL, value);
|
||||
}
|
||||
finally
|
||||
{
|
||||
context[CpuRegister.Rdi] = address;
|
||||
_ = KernelMemoryCompatExports.Free(context);
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user