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MikeyLITE69
52d2874fa8
## What The native backend runs guest code directly on the host CPU. When the host doesn't implement a BMI1/BMI2/ABM instruction that the PS5's Zen 2 cores do, it raises #UD (STATUS_ILLEGAL_INSTRUCTION). Today the vectored handler just logs the faulting bytes and gives up, so the title dies. This adds a software fallback. On an illegal-instruction fault we decode the opcode with Iced (the decoder already used elsewhere in the backend), evaluate it against the trapped register/memory state, write the result and flags back into the CONTEXT record, step RIP past the instruction, and resume. Instructions covered (32- and 64-bit): ANDN, BLSI, BLSMSK, BLSR, BEXTR, BZHI, TZCNT, LZCNT, RORX, SARX, SHLX, SHRX, PDEP, PEXT. ## Why Users on CPUs without these extensions currently can't get past code that uses them. This is a generic fix (no game-specific hacks) that improves compatibility on older hosts. MULX is intentionally left out for now — its dest_hi/dest_lo operand ordering is easy to get subtly wrong, so I'd rather add it separately with its own tests. ## How it's structured - `BmiInstructionEmulator` holds the pure bit/flag semantics with no dependency on the unsafe CONTEXT plumbing, so it can be unit-tested directly. - `DirectExecutionBackend.IllegalInstruction.cs` is the thin unsafe adapter (decode → read operands → emulate → write back → advance RIP). Anything it doesn't fully model returns false and falls through to the existing diagnostics unchanged, so it can never mis-handle an opcode it doesn't recognize. - One hook in `DirectExecutionBackend.Exceptions.cs`, next to the other TryRecover* calls. - Emits a single one-time "emulating in software" log line, not per-instruction spam. ## How I verified - Added xUnit tests covering every instruction in both widths plus the CF/ZF/SF/OF edge cases (src == 0, shift-count masking, index beyond operand width, etc.). - Cross-checked all the expected values against an independent reference implementation written from the Intel/AMD definitions; results match. - `dotnet build` + `dotnet test` pass locally. ## Notes New files follow .editorconfig (4-space, SPDX headers, REUSE-compliant).
363 lines
14 KiB
C#
363 lines
14 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using System.Threading;
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using Iced.Intel;
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using SharpEmu.Core.Cpu.Emulation;
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namespace SharpEmu.Core.Cpu.Native;
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// Software fallback for the BMI1/BMI2/ABM general-purpose-register instructions.
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//
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// Guest code runs natively, so the guest and host share the same virtual address space and the
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// same registers (the OS delivers them in the CONTEXT record on a fault). When the host CPU lacks
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// one of these extensions it raises #UD instead of executing the opcode; without this the title
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// simply aborts. Here we decode the faulting instruction, evaluate it against the trapped register
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// and memory state, write the result back into the CONTEXT, step RIP past the instruction and ask
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// the OS to continue. Only the register-only BMI/ABM forms are handled; anything else returns false
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// and falls through to the existing diagnostics unchanged, so this can never mis-handle an opcode it
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// does not fully model.
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public sealed partial class DirectExecutionBackend
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{
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// Windows x64 CONTEXT.EFlags lives just past the segment selectors. The GPR offsets it shares
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// with the rest of the backend are the CTX_* constants declared in DirectExecutionBackend.cs.
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private const int CTX_EFLAGS = 68;
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// STATUS_ILLEGAL_INSTRUCTION (#UD surfaced by the Windows vectored handler).
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private const uint StatusIllegalInstruction = 0xC000001Du;
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private const int MaxInstructionBytes = 15;
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// Instruction-window sizes tried in turn so a fault near a page boundary still decodes.
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private static readonly int[] DecodeWindowSizes = { MaxInstructionBytes, 11, 8, 4, 2 };
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private static int _bmiSoftwareFallbackAnnounced;
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private static long _bmiInstructionsEmulated;
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private unsafe bool TryRecoverIllegalInstruction(void* contextRecord, ulong rip)
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{
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if (!TryReadFaultingInstruction(rip, out var instruction))
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{
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return false;
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}
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if (instruction.Op0Kind != OpKind.Register ||
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!TryGetGprSlot(instruction.Op0Register, out var destOffset, out var size))
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{
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return false;
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}
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if (!TryEvaluate(contextRecord, in instruction, size, out var result, out var flagsChanged, out var eflags))
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{
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return false;
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}
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WriteCtxU64(contextRecord, destOffset, result);
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if (flagsChanged)
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{
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WriteCtxU32(contextRecord, CTX_EFLAGS, eflags);
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}
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WriteCtxU64(contextRecord, CTX_RIP, rip + (ulong)instruction.Length);
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Interlocked.Increment(ref _bmiInstructionsEmulated);
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if (Interlocked.Exchange(ref _bmiSoftwareFallbackAnnounced, 1) == 0)
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{
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Console.Error.WriteLine(
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"[LOADER][INFO] Host lacks a BMI/ABM extension used by the guest; " +
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"emulating those instructions in software.");
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}
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return true;
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}
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private unsafe bool TryEvaluate(
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void* contextRecord,
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in Instruction instruction,
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GprOperandSize size,
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out ulong result,
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out bool flagsChanged,
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out uint eflags)
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{
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result = 0;
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flagsChanged = false;
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eflags = ReadCtxU32(contextRecord, CTX_EFLAGS);
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switch (instruction.Mnemonic)
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{
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case Mnemonic.Andn:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var andnSrc1) ||
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!TryReadOperand(contextRecord, in instruction, 2, size, out var andnSrc2))
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{
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return false;
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}
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result = BmiInstructionEmulator.Andn(andnSrc1, andnSrc2, size, ref eflags);
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flagsChanged = true;
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return true;
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case Mnemonic.Blsi:
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case Mnemonic.Blsmsk:
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case Mnemonic.Blsr:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var blsSrc))
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{
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return false;
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}
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result = instruction.Mnemonic switch
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{
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Mnemonic.Blsi => BmiInstructionEmulator.Blsi(blsSrc, size, ref eflags),
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Mnemonic.Blsmsk => BmiInstructionEmulator.Blsmsk(blsSrc, size, ref eflags),
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_ => BmiInstructionEmulator.Blsr(blsSrc, size, ref eflags),
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};
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flagsChanged = true;
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return true;
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case Mnemonic.Bextr:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var bextrSrc) ||
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!TryReadOperand(contextRecord, in instruction, 2, size, out var bextrControl))
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{
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return false;
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}
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result = BmiInstructionEmulator.Bextr(bextrSrc, bextrControl, size, ref eflags);
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flagsChanged = true;
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return true;
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case Mnemonic.Bzhi:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var bzhiSrc) ||
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!TryReadOperand(contextRecord, in instruction, 2, size, out var bzhiIndex))
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{
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return false;
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}
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result = BmiInstructionEmulator.Bzhi(bzhiSrc, bzhiIndex, size, ref eflags);
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flagsChanged = true;
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return true;
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case Mnemonic.Tzcnt:
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case Mnemonic.Lzcnt:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var cntSrc))
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{
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return false;
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}
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result = instruction.Mnemonic == Mnemonic.Tzcnt
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? BmiInstructionEmulator.Tzcnt(cntSrc, size, ref eflags)
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: BmiInstructionEmulator.Lzcnt(cntSrc, size, ref eflags);
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flagsChanged = true;
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return true;
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case Mnemonic.Rorx:
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if (instruction.Op2Kind != OpKind.Immediate8 ||
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!TryReadOperand(contextRecord, in instruction, 1, size, out var rorxSrc))
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{
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return false;
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}
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result = BmiInstructionEmulator.Rorx(rorxSrc, instruction.Immediate8, size);
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return true;
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case Mnemonic.Sarx:
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case Mnemonic.Shlx:
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case Mnemonic.Shrx:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var shiftSrc) ||
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!TryReadOperand(contextRecord, in instruction, 2, size, out var shiftCount))
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{
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return false;
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}
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result = instruction.Mnemonic switch
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{
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Mnemonic.Sarx => BmiInstructionEmulator.Sarx(shiftSrc, (int)shiftCount, size),
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Mnemonic.Shlx => BmiInstructionEmulator.Shlx(shiftSrc, (int)shiftCount, size),
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_ => BmiInstructionEmulator.Shrx(shiftSrc, (int)shiftCount, size),
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};
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return true;
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case Mnemonic.Pdep:
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case Mnemonic.Pext:
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if (!TryReadOperand(contextRecord, in instruction, 1, size, out var packSrc) ||
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!TryReadOperand(contextRecord, in instruction, 2, size, out var packMask))
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{
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return false;
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}
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result = instruction.Mnemonic == Mnemonic.Pdep
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? BmiInstructionEmulator.Pdep(packSrc, packMask, size)
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: BmiInstructionEmulator.Pext(packSrc, packMask, size);
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return true;
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default:
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return false;
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}
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}
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private unsafe bool TryReadFaultingInstruction(ulong rip, out Instruction instruction)
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{
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// Try the full instruction window first, then shrink so a fault near the end of a mapped
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// page (where fewer than 15 bytes are readable) still decodes.
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foreach (var attempt in DecodeWindowSizes)
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{
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var buffer = new byte[attempt];
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if (!TryReadHostBytes(rip, buffer))
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{
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continue;
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}
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var decoder = Decoder.Create(64, new ByteArrayCodeReader(buffer));
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decoder.IP = rip;
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decoder.Decode(out instruction);
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if (instruction.Code != Code.INVALID && instruction.Length > 0 && instruction.Length <= attempt)
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{
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return true;
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}
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}
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instruction = default;
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return false;
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}
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private unsafe bool TryReadOperand(
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void* contextRecord,
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in Instruction instruction,
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int operandIndex,
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GprOperandSize size,
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out ulong value)
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{
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value = 0;
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switch (instruction.GetOpKind(operandIndex))
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{
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case OpKind.Register:
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if (!TryGetGprSlot(instruction.GetOpRegister(operandIndex), out var offset, out _))
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{
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return false;
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}
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var raw = ReadCtxU64(contextRecord, offset);
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value = size == GprOperandSize.Bits64 ? raw : raw & 0xFFFF_FFFFUL;
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return true;
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case OpKind.Memory:
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if (!TryComputeMemoryAddress(contextRecord, in instruction, out var address))
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{
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return false;
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}
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var byteCount = size == GprOperandSize.Bits64 ? 8 : 4;
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var buffer = new byte[byteCount];
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if (!TryReadHostBytes(address, buffer))
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{
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return false;
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}
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value = byteCount == 8
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? BinaryPrimitives.ReadUInt64LittleEndian(buffer)
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: BinaryPrimitives.ReadUInt32LittleEndian(buffer);
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return true;
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default:
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return false;
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}
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}
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private unsafe bool TryComputeMemoryAddress(void* contextRecord, in Instruction instruction, out ulong address)
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{
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address = 0;
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// FS/GS-relative operands need the guest segment base, which is not modelled here.
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if (instruction.SegmentPrefix != Register.None)
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{
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return false;
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}
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if (instruction.IsIPRelativeMemoryOperand)
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{
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address = instruction.IPRelativeMemoryAddress;
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return true;
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}
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var effective = instruction.MemoryDisplacement64;
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if (instruction.MemoryBase != Register.None)
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{
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if (!TryGetGpr64Offset(instruction.MemoryBase, out var baseOffset))
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{
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return false;
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}
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effective += ReadCtxU64(contextRecord, baseOffset);
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}
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if (instruction.MemoryIndex != Register.None)
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{
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if (!TryGetGpr64Offset(instruction.MemoryIndex, out var indexOffset))
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{
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return false;
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}
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effective += ReadCtxU64(contextRecord, indexOffset) * (ulong)instruction.MemoryIndexScale;
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}
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address = effective;
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return true;
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}
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// Maps a 32- or 64-bit GPR to its CONTEXT offset and reports the operand width it implies.
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private static bool TryGetGprSlot(Register register, out int offset, out GprOperandSize size)
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{
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switch (register)
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{
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case Register.EAX: offset = CTX_RAX; size = GprOperandSize.Bits32; return true;
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case Register.ECX: offset = CTX_RCX; size = GprOperandSize.Bits32; return true;
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case Register.EDX: offset = CTX_RDX; size = GprOperandSize.Bits32; return true;
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case Register.EBX: offset = CTX_RBX; size = GprOperandSize.Bits32; return true;
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case Register.ESP: offset = CTX_RSP; size = GprOperandSize.Bits32; return true;
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case Register.EBP: offset = CTX_RBP; size = GprOperandSize.Bits32; return true;
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case Register.ESI: offset = CTX_RSI; size = GprOperandSize.Bits32; return true;
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case Register.EDI: offset = CTX_RDI; size = GprOperandSize.Bits32; return true;
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case Register.R8D: offset = CTX_R8; size = GprOperandSize.Bits32; return true;
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case Register.R9D: offset = CTX_R9; size = GprOperandSize.Bits32; return true;
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case Register.R10D: offset = CTX_R10; size = GprOperandSize.Bits32; return true;
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case Register.R11D: offset = CTX_R11; size = GprOperandSize.Bits32; return true;
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case Register.R12D: offset = CTX_R12; size = GprOperandSize.Bits32; return true;
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case Register.R13D: offset = CTX_R13; size = GprOperandSize.Bits32; return true;
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case Register.R14D: offset = CTX_R14; size = GprOperandSize.Bits32; return true;
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case Register.R15D: offset = CTX_R15; size = GprOperandSize.Bits32; return true;
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default:
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if (TryGetGpr64Offset(register, out offset))
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{
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size = GprOperandSize.Bits64;
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return true;
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}
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size = GprOperandSize.Bits32;
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return false;
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}
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}
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private static bool TryGetGpr64Offset(Register register, out int offset)
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{
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switch (register)
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{
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case Register.RAX: offset = CTX_RAX; return true;
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case Register.RCX: offset = CTX_RCX; return true;
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case Register.RDX: offset = CTX_RDX; return true;
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case Register.RBX: offset = CTX_RBX; return true;
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case Register.RSP: offset = CTX_RSP; return true;
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case Register.RBP: offset = CTX_RBP; return true;
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case Register.RSI: offset = CTX_RSI; return true;
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case Register.RDI: offset = CTX_RDI; return true;
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case Register.R8: offset = CTX_R8; return true;
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case Register.R9: offset = CTX_R9; return true;
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case Register.R10: offset = CTX_R10; return true;
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case Register.R11: offset = CTX_R11; return true;
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case Register.R12: offset = CTX_R12; return true;
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case Register.R13: offset = CTX_R13; return true;
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case Register.R14: offset = CTX_R14; return true;
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case Register.R15: offset = CTX_R15; return true;
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default: offset = 0; return false;
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}
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}
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}
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