mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-31 23:19:44 +08:00
db4339f698
* fix(kernel): implement APR ResolveFilepathsWithPrefixToIdsAndFileSizes Resource streamers resolve relative paths against a shared prefix; without this HLE every call returned NOT_FOUND and assets never got real ids/sizes. * fix(remoteplay): stub Initialize and GetConnectionStatus as disconnected Titles probe Remote Play during pad/network bring-up; unresolved imports returned NOT_FOUND. Report initialized + disconnected so callers take the normal offline path. * fix(agc): accept Gen5 hull shaders that omit PGM_LO/HI in CreateShader Type-5 headers can start with RSRC1/RSRC2; rejecting them left null handles and Main Thread AVs. Scan the SH table and skip PGM patch when absent. Co-authored-by: Cursor <cursoragent@cursor.com> * fix(kernel): reject getdents on file fds and emit . / .. for empty dirs Returning rax=0 for non-directory or empty listings looked like EOF and let GTA treat the fd as a pointer (fiWriteAsyncDataWorker AV at 0xB1). * fix(hle): enable GuestImageWriteTracker CPU sync on Windows Windows previously hard-disabled the tracker, so CPU-written guest planes never marked dirty and host textures stayed empty. Arm pages with VirtualProtect, handle write AVs in VEH, and warm/test on VirtualAlloc memory so protect cannot poison the CRT heap. * fix(agc): skip CB metadata draws for EliminateFastClear/Fmask/DCC CB_COLOR_CONTROL modes 2/5/6 are colour-buffer metadata ops; applying the bound shader as a normal colour draw corrupts subsequent composites. Decode MODE from bits [6:4] and return before translate. * fix(agc): merge Prospero attrib-table formats onto IR vertex inputs IR-discovered BufferLoadFormat often keeps a stale float sharp format; patch DataFormat/offset from the AGC attrib table (semantic index), allow offen fetches, and map quirks 113/121 through NarrowVk for host vertex input. * fix(audio): harden AudioOut2 stack out-buffer writes against canary smash Titles that stack-allocate AudioOut2 outs next to the frame canary were corrupted by oversized or mistyped HLE writes; keep ContextPush pacing. * Revert "fix(memory): reserve only large regions (#608)" This reverts commit8f9456229a. * fix(gpu): decode Gen5 R16 and RG32 render-target formats * fix(audio): AudioOut2 host beds, deeper waveOut queue, AJM MP3 GTA V Enhanced routes intro/menu audio through AudioOut2 and FMOD's AJM MP3 path. Wire PortCreate/PortSetAttributes/ContextPush to dual host stereo streams, deepen WinMM queue to 128KiB, and decode AJM codec 0 with a stateful NLayer helper so menu music is not silent. * fix(agc): map PS interpolants via SPI_PS_INPUT_CNTL semantics Identity ATTR→param wiring ignored hardware remapping, so UI draws got wrong (or empty) interpolants. Pack CNTL from matched PS/GS semantics, thread it into Vulkan/Metal as Location/Flat, and fingerprint it in the graphics shader cache key. * fix(agc): rect-list/NGG strips, Index8 expand, and GE_INDX_OFFSET NGG single-rect UI needs triangle-strip expansion; Prospero Index8 must expand to host u16; glyphs need base vertex from GE_INDX_OFFSET. Skip param-less rect-lists instead of inventing colour draws. * fix(np): report GTA Story Mode addcont entitlements as owned NpEntitlementAccess was returning an empty add-on list, so GTA V Enhanced offered Buy Story Mode. Publish the installed license labels and stub premium-event registration so offline sessions take the owned path. * fix(cpu): prefer native workers for all guest entry stubs Route thread entry, continuation, and main entry through RunGuestEntryStub so guest stubs are not invoked above CLR-managed frames (UnmanagedCallersOnly FailFast). Keep requireNativeWorker for tbb_thead; other paths prefer workers with calli fallback. * fix(agc): implement Rewind/Jump writers and IT_REWIND waits GTA Subrender AVs came from AcbJumpGetSize / DcbRewind returning NOT_FOUND as packet sizes. Add IT_REWIND and INDIRECT_BUFFER writers, patch SetRewindState into the GPU wait registry, and nest-parse 4-dword jumps. * fix(gpu): use AddrLib ExactXor for Gen5 Standard256B (mode 1) Mode 5 already had Standard4K ExactXor; mode 1 still used the generic StandardSwizzle block table, which mis-detiles Gen5 UI atlases. * Revert "fix(cpu): prefer native workers for all guest entry stubs" This reverts commit31c4db0d38. * fix(memory): commit-first large maps; reserve only on failure Replace the #608 always-reserve-only exact-map path with allocate-first and lazy reserve fallback when a huge non-exec commit cannot be satisfied. Prime and widen GetPointer commit so the fallback path is safer for native walkers. Drops the need for a hard #608 revert. * [Agc] Implement fused shader half exports * fix(agc): accept optional hull state in CreatePrimState Port the CreatePrimState hull-optional path from #583 so fused HS pipelines (GTA) are not rejected with INVALID_ARGUMENT. Geometry-derived CX/UC writes are unchanged; hull is traced only. * fix(videoout): restore thread-safe VulkanHostBufferPool (#564) The6db095ewipe dropped CasualcoderDev's lock-ordering-safe pool. Concurrent Return/TryTake without the gate races after the first present and can hang the submit path. * Revert "fix(agc): implement Rewind/Jump writers and IT_REWIND waits" This reverts commitbec77bf083. * test(memory): align lazy-commit expectations with commit-first policy Fake hosts must reject Allocate so reserve-only paths still run, and GetPointer asserts the 32 MiB prime range including AlignUp spill. * diag(gpu): log guest-queue backlog breakdown under backpressure Rate-limit top work types and ordered debugName prefixes when the Vulkan guest work queue stalls, so North Yankton logs show acquire/label vs draw traffic instead of only VulkanOrderedGuestAction. * perf(agc): coalesce acquire flushes and batch non-DMA label wakes Flush pending ACQUIRE_MEM invalidation at draw/dispatch/dma/flip boundaries instead of before every packet, and complete release/write-data producers in the same ordered action so load paths enqueue far fewer VulkanOrderedGuestAction items. * perf(gpu): wait for ordered-action fences and keep draining sync On Windows/Linux, block briefly for queue-visibility fences instead of deferring the whole logical queue for the tick. Prefer ordered sync/flip heads under backlog pressure, and keep macOS non-blocking defer behavior. * perf(gpu): raise sync-item ceiling above payload guest-work cap Apply SHARPEMU_PENDING_GUEST_WORK_ITEMS mainly to compute/draw/image payload work, and allow a higher SHARPEMU_PENDING_GUEST_SYNC_ITEMS ceiling for zero-payload ordered actions and flip markers. Keep the byte budget as the RAM safety valve. * fix(gta): stub Voice ports and implement sceKernelCheckReachability Resolve North Yankton-path Voice Create/Delete/Connect/Disconnect/End NIDs and EnumerationThread reachability checks so leftover unresolved imports are not on the critical path. * diag(gta): arm flip/present/wait probes after North Audio Rate-limited load_progress TRACE for flip submit, ordered flip enqueue, present taken/not-taken, and GPU wait backlog so North Yankton freezes can be classified without full AGC tracing. * fix(ampr): restore sequential offset=-1 reads for streamer packs Re-wire PakDirectoryTracker into sceAmprAprCommandBufferReadFile (dropped in #216) so RAGE sequential pack reads no longer fail while the North Yankton UI keeps flipping. Also rate-limit CheckReachability miss paths for EnumerationThread diagnosis. * fix(hle/videoout): Windows GuestImage opt-in and keep GTA intro without sync Default the tracker off on Windows to avoid VirtualProtect thrash, gate AGC texel-copy skips on Enabled so guest Bink planes keep shipping pixels, and drain CPU-written images on the present thread when sync is opted in. * fix(videoout): probe guest content when tracker off so UI can skip copies Restores upload-known/texture-cache skips for Dead Cells menus, and uses a sparse guest-memory fingerprint when GuestImageWriteTracker is disabled so CPU-updated Bink planes still force texel copies for GTA intro. * fix(audio): keep 128KiB host queue AudioOut2-only Restore the default 32 KiB (~171 ms) PCM bed for classic AudioOut so titles like Dreaming Sarah stay in sync; only AudioOut2 opens the deeper queue needed for bursty FMOD Push on GTA. --------- Co-authored-by: samto6 <123419830+samto6@users.noreply.github.com>
1059 lines
36 KiB
C#
1059 lines
36 KiB
C#
// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using SharpEmu.HLE;
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using SharpEmu.Libs.Kernel;
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using System.Buffers;
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using System.Buffers.Binary;
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using System.Collections.Concurrent;
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using Microsoft.Win32.SafeHandles;
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namespace SharpEmu.Libs.Ampr;
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public static class AmprExports
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{
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private const int CommandBufferHeaderSize = 0x28;
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private const ulong CommandBufferSelfOffset = 0x00;
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private const ulong CommandBufferDataOffset = 0x08;
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private const ulong CommandBufferSizeOffset = 0x10;
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private const ulong CommandBufferAux0Offset = 0x18;
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private const ulong CommandBufferAux1Offset = 0x20;
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private const ulong ReadFileRecordSize = 0x30;
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private const ulong KernelEventQueueRecordSize = 0x30;
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private const ulong WriteAddressRecordSize = 0x20;
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private const uint ReadFileRecordType = 1;
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private const uint KernelEventQueueRecordType = 2;
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private const uint WriteAddressRecordType = 3;
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private static readonly ConcurrentDictionary<ulong, CommandBufferState> _commandBuffers = new();
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private static readonly ConcurrentDictionary<string, Lazy<CachedHostFile>> _hostFileCache = new(StringComparer.OrdinalIgnoreCase);
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private static readonly bool _traceAmpr =
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string.Equals(Environment.GetEnvironmentVariable("SHARPEMU_LOG_AMPR"), "1", StringComparison.Ordinal);
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private static readonly bool _traceAmprReads =
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_traceAmpr ||
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string.Equals(Environment.GetEnvironmentVariable("SHARPEMU_LOG_AMPR_READS"), "1", StringComparison.Ordinal);
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private sealed class CommandBufferState
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{
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public ulong Buffer;
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public ulong Size;
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public ulong WriteOffset;
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public ulong CommandCount;
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}
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private sealed class CachedHostFile
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{
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public CachedHostFile(string path)
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{
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Handle = File.OpenHandle(
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path,
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FileMode.Open,
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FileAccess.Read,
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FileShare.ReadWrite | FileShare.Delete,
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FileOptions.RandomAccess);
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Length = RandomAccess.GetLength(Handle);
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}
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public SafeFileHandle Handle { get; }
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public long Length { get; }
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}
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[SysAbiExport(
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Nid = "8aI7R7WaOlc",
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ExportName = "sceAmprCommandBufferConstructor",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int CommandBufferConstructor(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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var buffer = ctx[CpuRegister.Rsi];
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var size = ctx[CpuRegister.Rdx];
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if (commandBuffer == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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if (!InitializeCommandBuffer(ctx, commandBuffer, buffer, size, aux0: 0, aux1: 0, clear: true))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmpr(ctx, "ctor", commandBuffer, buffer, size);
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ctx[CpuRegister.Rax] = commandBuffer;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "a8uLzYY--tM",
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ExportName = "sceAmprAprCommandBufferConstructor",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int AprCommandBufferConstructor(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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var aux0 = ctx[CpuRegister.Rsi];
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var aux1 = ctx[CpuRegister.Rdx];
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if (commandBuffer == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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if (!InitializeCommandBuffer(ctx, commandBuffer, buffer: 0, size: 0, aux0, aux1, clear: false))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmpr(ctx, "apr_ctor", commandBuffer, aux0, aux1);
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ctx[CpuRegister.Rax] = commandBuffer;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "Qs1xtplKo0U",
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ExportName = "sceAmprAprCommandBufferDestructor",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int AprCommandBufferDestructor(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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if (commandBuffer == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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Span<byte> auxiliaryPointers = stackalloc byte[sizeof(ulong) * 2];
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auxiliaryPointers.Clear();
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if (!ctx.Memory.TryWrite(commandBuffer + CommandBufferAux0Offset, auxiliaryPointers))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmpr(ctx, "apr_dtor", commandBuffer, 0, 0);
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "GuchCTefuZw",
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ExportName = "sceAmprCommandBufferDestructor",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int CommandBufferDestructor(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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if (commandBuffer == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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if (!WriteVisibleCommandBufferPointers(ctx, commandBuffer, buffer: 0, size: 0))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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_commandBuffers.TryRemove(commandBuffer, out _);
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TraceAmpr(ctx, "dtor", commandBuffer, 0, 0);
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "N-FSPA4S3nI",
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ExportName = "sceAmprCommandBufferSetBuffer",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int CommandBufferSetBuffer(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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var buffer = ctx[CpuRegister.Rsi];
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var size = ctx[CpuRegister.Rdx];
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if (commandBuffer == 0)
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
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}
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if (!WriteCommandBufferPointers(ctx, commandBuffer, buffer, size))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmpr(ctx, "set_buffer", commandBuffer, buffer, size);
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "baQO9ez2gL4",
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ExportName = "sceAmprCommandBufferReset",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int CommandBufferReset(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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if (commandBuffer == 0)
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
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}
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Span<byte> bufferPointers = stackalloc byte[sizeof(ulong) * 2];
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if (!ctx.Memory.TryRead(commandBuffer + CommandBufferDataOffset, bufferPointers))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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var buffer = BinaryPrimitives.ReadUInt64LittleEndian(bufferPointers);
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var size = BinaryPrimitives.ReadUInt64LittleEndian(bufferPointers[sizeof(ulong)..]);
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if (
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!WriteCommandBufferPointers(ctx, commandBuffer, buffer, size, writeOffset: 0))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmpr(ctx, "reset", commandBuffer, buffer, size);
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "ULvXMDz56po",
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ExportName = "sceAmprCommandBufferClearBuffer",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int CommandBufferClearBuffer(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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if (commandBuffer == 0)
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
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}
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if (!TryGetCommandBufferState(ctx, commandBuffer, out var buffer, out var size, out _) ||
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!WriteVisibleCommandBufferPointers(ctx, commandBuffer, buffer: 0, size: 0))
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{
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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_commandBuffers.TryRemove(commandBuffer, out _);
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TraceAmpr(ctx, "clear_buffer", commandBuffer, buffer, size);
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ctx[CpuRegister.Rax] = buffer;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "mQ16-QdKv7k",
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ExportName = "sceAmprAprCommandBufferReadFile",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int AprCommandBufferReadFile(CpuContext ctx)
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{
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var commandBuffer = ctx[CpuRegister.Rdi];
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var fileId = unchecked((uint)ctx[CpuRegister.Rcx]);
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var destination = ctx[CpuRegister.R8];
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var size = ctx[CpuRegister.R9];
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if (commandBuffer == 0 || (destination == 0 && size != 0))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
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}
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if (!ctx.TryReadUInt64(ctx[CpuRegister.Rsp] + sizeof(ulong), out var fileOffset))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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if (!AmprFileRegistry.TryGetHostPath(fileId, out var hostPath))
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{
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TraceAmprRead(ctx, commandBuffer, fileId, destination, size, fileOffset, bytesRead: 0, hostPath, (int)OrbisGen2Result.ORBIS_GEN2_ERROR_NOT_FOUND);
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_NOT_FOUND;
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}
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// Offset -1 means "continue after the previous read of this file id".
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// #216 dropped this wiring; without it sequential pack/streamer reads
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// fail as INVALID_ARGUMENT and RAGE load jobs never complete while the
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// North Yankton UI keeps flipping.
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if (fileOffset == unchecked((ulong)(long)-1))
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{
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fileOffset = PakDirectoryTracker.ResolveSequentialOffset(fileId, size);
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}
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else if (fileOffset > long.MaxValue)
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{
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fileOffset = 0;
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}
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var result = TryReadFileToGuestMemory(ctx, hostPath, fileOffset, destination, size, out var bytesRead);
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if (result != (int)OrbisGen2Result.ORBIS_GEN2_OK)
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{
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TraceAmprRead(ctx, commandBuffer, fileId, destination, size, fileOffset, bytesRead, hostPath, result);
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return result;
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}
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PakDirectoryTracker.OnReadCompleted(ctx, fileId, destination, fileOffset, bytesRead);
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if (!AppendReadFileRecord(ctx, commandBuffer, fileId, destination, size, fileOffset, bytesRead))
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{
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return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
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}
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TraceAmprRead(ctx, commandBuffer, fileId, destination, size, fileOffset, bytesRead, hostPath, (int)OrbisGen2Result.ORBIS_GEN2_OK);
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ctx[CpuRegister.Rax] = 0;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "vWU-odnS+fU",
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ExportName = "sceAmprMeasureCommandSizeReadFile",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int MeasureCommandSizeReadFile(CpuContext ctx)
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{
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TraceAmpr(ctx, "measure_read_file", 0, ReadFileRecordSize, 0);
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ctx[CpuRegister.Rax] = ReadFileRecordSize;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "sSAUCCU1dv4",
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ExportName = "sceAmprMeasureCommandSizeWriteKernelEventQueue_04_00",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int MeasureCommandSizeWriteKernelEventQueue0400(CpuContext ctx)
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{
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TraceAmpr(ctx, "measure_write_equeue", 0, KernelEventQueueRecordSize, 0);
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ctx[CpuRegister.Rax] = KernelEventQueueRecordSize;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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[SysAbiExport(
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Nid = "Zi3dBUjgyXI",
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ExportName = "sceAmprMeasureCommandSizeWriteKernelEventQueueOnCompletion",
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Target = Generation.Gen5,
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LibraryName = "libSceAmpr")]
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public static int MeasureCommandSizeWriteKernelEventQueueOnCompletion(CpuContext ctx)
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{
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TraceAmpr(ctx, "measure_write_equeue_complete", 0, KernelEventQueueRecordSize, 0);
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ctx[CpuRegister.Rax] = KernelEventQueueRecordSize;
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return (int)OrbisGen2Result.ORBIS_GEN2_OK;
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}
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|
|
[SysAbiExport(
|
|
Nid = "C+IEj+BsAFM",
|
|
ExportName = "sceAmprMeasureCommandSizeWriteAddressOnCompletion",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int MeasureCommandSizeWriteAddressOnCompletion(CpuContext ctx)
|
|
{
|
|
TraceAmpr(ctx, "measure_write_address_complete", 0, WriteAddressRecordSize, 0);
|
|
ctx[CpuRegister.Rax] = WriteAddressRecordSize;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "4fgtGfXDrFc",
|
|
ExportName = "sceAmprMeasureCommandSizeWriteAddress_04_00",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int MeasureCommandSizeWriteAddress0400(CpuContext ctx)
|
|
{
|
|
TraceAmpr(ctx, "measure_write_address", 0, WriteAddressRecordSize, 0);
|
|
ctx[CpuRegister.Rax] = WriteAddressRecordSize;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "tZDDEo2tE5k",
|
|
ExportName = "sceAmprCommandBufferGetSize",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferGetSize(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!TryGetCommandBufferState(ctx, commandBuffer, out _, out var size, out _))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "get_size", commandBuffer, size, 0);
|
|
ctx[CpuRegister.Rax] = size;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "GnxKOHEawhk",
|
|
ExportName = "sceAmprCommandBufferGetCurrentOffset",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferGetCurrentOffset(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!TryGetCommandBufferOffset(ctx, commandBuffer, out var offset))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "get_offset", commandBuffer, offset, 0);
|
|
ctx[CpuRegister.Rax] = offset;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "gzndltBEzWc",
|
|
ExportName = "sceAmprCommandBufferGetNumCommands",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferGetNumCommands(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!TryGetCommandBufferState(ctx, commandBuffer, out _, out _, out var state) || state is null)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
ulong commandCount;
|
|
lock (state)
|
|
{
|
|
commandCount = state.CommandCount;
|
|
}
|
|
|
|
TraceAmpr(ctx, "get_num_commands", commandBuffer, commandCount, 0);
|
|
ctx[CpuRegister.Rax] = commandCount;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "H896Pt-yB4I",
|
|
ExportName = "sceAmprCommandBufferWriteKernelEventQueue_04_00",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferWriteKernelEventQueue0400(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
var equeue = ctx[CpuRegister.Rsi];
|
|
var ident = ctx[CpuRegister.Rdx];
|
|
var completionToken = ctx[CpuRegister.Rcx];
|
|
var userData = ctx[CpuRegister.R8];
|
|
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!AppendKernelEventQueueRecord(
|
|
ctx,
|
|
commandBuffer,
|
|
equeue,
|
|
ident,
|
|
completionToken,
|
|
userData))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "write_equeue", commandBuffer, ident, completionToken);
|
|
ctx[CpuRegister.Rax] = 0;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "o67gODLFpls",
|
|
ExportName = "sceAmprCommandBufferWriteKernelEventQueueOnCompletion",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferWriteKernelEventQueueOnCompletion(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
var equeue = ctx[CpuRegister.Rsi];
|
|
var ident = ctx[CpuRegister.Rdx];
|
|
var completionToken = ctx[CpuRegister.Rcx];
|
|
var userData = ctx[CpuRegister.R8];
|
|
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!AppendKernelEventQueueRecord(
|
|
ctx,
|
|
commandBuffer,
|
|
equeue,
|
|
ident,
|
|
completionToken,
|
|
userData))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "write_equeue_complete", commandBuffer, ident, completionToken);
|
|
ctx[CpuRegister.Rax] = 0;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "sJXyWHjP-F8",
|
|
ExportName = "sceAmprCommandBufferWriteAddressOnCompletion",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferWriteAddressOnCompletion(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
var address = ctx[CpuRegister.Rsi];
|
|
var value = ctx[CpuRegister.Rdx];
|
|
|
|
if (commandBuffer == 0 || address == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!AppendWriteAddressRecord(ctx, commandBuffer, address, value))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "write_address_complete", commandBuffer, address, value);
|
|
ctx[CpuRegister.Rax] = 0;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
[SysAbiExport(
|
|
Nid = "j0+3uJMxYJY",
|
|
ExportName = "sceAmprCommandBufferWriteAddress_04_00",
|
|
Target = Generation.Gen5,
|
|
LibraryName = "libSceAmpr")]
|
|
public static int CommandBufferWriteAddress0400(CpuContext ctx)
|
|
{
|
|
var commandBuffer = ctx[CpuRegister.Rdi];
|
|
var address = ctx[CpuRegister.Rsi];
|
|
var value = ctx[CpuRegister.Rdx];
|
|
|
|
if (commandBuffer == 0 || address == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!AppendWriteAddressRecord(ctx, commandBuffer, address, value))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
TraceAmpr(ctx, "write_address", commandBuffer, address, value);
|
|
ctx[CpuRegister.Rax] = 0;
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
public static int CompleteCommandBuffer(CpuContext ctx, ulong commandBuffer)
|
|
{
|
|
if (commandBuffer == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
if (!TryGetCommandBufferState(ctx, commandBuffer, out var buffer, out _, out var state) || state is null)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
ulong writeOffset;
|
|
lock (state)
|
|
{
|
|
writeOffset = state.WriteOffset;
|
|
}
|
|
|
|
var offset = 0UL;
|
|
while (offset < writeOffset)
|
|
{
|
|
if (!TryReadUInt32(ctx, buffer + offset, out var recordType))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
switch (recordType)
|
|
{
|
|
case ReadFileRecordType:
|
|
offset += ReadFileRecordSize;
|
|
break;
|
|
|
|
case KernelEventQueueRecordType:
|
|
if (!CompleteKernelEventQueueRecord(ctx, buffer + offset))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
offset += KernelEventQueueRecordSize;
|
|
break;
|
|
|
|
case WriteAddressRecordType:
|
|
if (!CompleteWriteAddressRecord(ctx, buffer + offset))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
offset += WriteAddressRecordSize;
|
|
break;
|
|
|
|
default:
|
|
TraceAmpr(ctx, "complete_unknown", commandBuffer, recordType, offset);
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
}
|
|
|
|
TraceAmpr(ctx, "complete", commandBuffer, buffer, writeOffset);
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
private static bool InitializeCommandBuffer(
|
|
CpuContext ctx,
|
|
ulong commandBuffer,
|
|
ulong buffer,
|
|
ulong size,
|
|
ulong aux0,
|
|
ulong aux1,
|
|
bool clear)
|
|
{
|
|
Span<byte> header = stackalloc byte[CommandBufferHeaderSize];
|
|
if (clear)
|
|
{
|
|
header.Clear();
|
|
}
|
|
else
|
|
{
|
|
if (!ctx.Memory.TryRead(commandBuffer, header))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
buffer = BinaryPrimitives.ReadUInt64LittleEndian(header[(int)CommandBufferDataOffset..]);
|
|
size = BinaryPrimitives.ReadUInt64LittleEndian(header[(int)CommandBufferSizeOffset..]);
|
|
}
|
|
|
|
BinaryPrimitives.WriteUInt64LittleEndian(header[(int)CommandBufferSelfOffset..], commandBuffer);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(header[(int)CommandBufferDataOffset..], buffer);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(header[(int)CommandBufferSizeOffset..], size);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(header[(int)CommandBufferAux0Offset..], aux0);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(header[(int)CommandBufferAux1Offset..], aux1);
|
|
if (!ctx.Memory.TryWrite(commandBuffer, header))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
UpdateCommandBufferState(commandBuffer, buffer, size, writeOffset: 0);
|
|
return true;
|
|
}
|
|
|
|
private static bool WriteCommandBufferPointers(CpuContext ctx, ulong commandBuffer, ulong buffer, ulong size)
|
|
{
|
|
return WriteCommandBufferPointers(ctx, commandBuffer, buffer, size, writeOffset: 0);
|
|
}
|
|
|
|
private static bool WriteCommandBufferPointers(CpuContext ctx, ulong commandBuffer, ulong buffer, ulong size, ulong writeOffset)
|
|
{
|
|
if (!WriteVisibleCommandBufferPointers(ctx, commandBuffer, buffer, size))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
UpdateCommandBufferState(commandBuffer, buffer, size, writeOffset);
|
|
|
|
return true;
|
|
}
|
|
|
|
private static bool WriteVisibleCommandBufferPointers(CpuContext ctx, ulong commandBuffer, ulong buffer, ulong size)
|
|
{
|
|
Span<byte> pointers = stackalloc byte[sizeof(ulong) * 3];
|
|
BinaryPrimitives.WriteUInt64LittleEndian(pointers, commandBuffer);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(pointers[sizeof(ulong)..], buffer);
|
|
BinaryPrimitives.WriteUInt64LittleEndian(pointers[(sizeof(ulong) * 2)..], size);
|
|
return ctx.Memory.TryWrite(commandBuffer + CommandBufferSelfOffset, pointers);
|
|
}
|
|
|
|
private static void UpdateCommandBufferState(
|
|
ulong commandBuffer,
|
|
ulong buffer,
|
|
ulong size,
|
|
ulong writeOffset)
|
|
{
|
|
var state = _commandBuffers.GetOrAdd(commandBuffer, static _ => new CommandBufferState());
|
|
lock (state)
|
|
{
|
|
state.Buffer = buffer;
|
|
state.Size = size;
|
|
state.WriteOffset = writeOffset;
|
|
state.CommandCount = 0;
|
|
}
|
|
}
|
|
|
|
private static bool TryGetCommandBufferState(
|
|
CpuContext ctx,
|
|
ulong commandBuffer,
|
|
out ulong buffer,
|
|
out ulong size,
|
|
out CommandBufferState? state)
|
|
{
|
|
if (_commandBuffers.TryGetValue(commandBuffer, out state))
|
|
{
|
|
lock (state)
|
|
{
|
|
buffer = state.Buffer;
|
|
size = state.Size;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
Span<byte> pointers = stackalloc byte[sizeof(ulong) * 2];
|
|
if (ctx.Memory.TryRead(commandBuffer + CommandBufferDataOffset, pointers))
|
|
{
|
|
buffer = BinaryPrimitives.ReadUInt64LittleEndian(pointers);
|
|
size = BinaryPrimitives.ReadUInt64LittleEndian(pointers[sizeof(ulong)..]);
|
|
state = _commandBuffers.GetOrAdd(commandBuffer, static _ => new CommandBufferState());
|
|
lock (state)
|
|
{
|
|
state.Buffer = buffer;
|
|
state.Size = size;
|
|
state.WriteOffset = 0;
|
|
state.CommandCount = 0;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
buffer = 0;
|
|
size = 0;
|
|
state = null;
|
|
return false;
|
|
}
|
|
|
|
private static bool TryGetCommandBufferOffset(CpuContext ctx, ulong commandBuffer, out ulong offset)
|
|
{
|
|
if (!TryGetCommandBufferState(ctx, commandBuffer, out _, out _, out var state) || state is null)
|
|
{
|
|
offset = 0;
|
|
return false;
|
|
}
|
|
|
|
lock (state)
|
|
{
|
|
offset = state.WriteOffset;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
private static int TryReadFileToGuestMemory(
|
|
CpuContext ctx,
|
|
string hostPath,
|
|
ulong fileOffset,
|
|
ulong destination,
|
|
ulong size,
|
|
out ulong bytesRead)
|
|
{
|
|
bytesRead = 0;
|
|
if (size == 0)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
if (fileOffset > long.MaxValue)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
const int ChunkSize = 1024 * 1024;
|
|
var buffer = ArrayPool<byte>.Shared.Rent((int)Math.Min((ulong)ChunkSize, size));
|
|
|
|
try
|
|
{
|
|
if (!TryGetCachedHostFile(hostPath, out var cachedFile, out var openResult))
|
|
{
|
|
return openResult;
|
|
}
|
|
|
|
if (fileOffset >= (ulong)cachedFile.Length)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
while (bytesRead < size)
|
|
{
|
|
if (bytesRead > ulong.MaxValue - fileOffset)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
var absoluteOffset = fileOffset + bytesRead;
|
|
if (absoluteOffset > long.MaxValue)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT;
|
|
}
|
|
|
|
var request = (int)Math.Min((ulong)buffer.Length, size - bytesRead);
|
|
var read = RandomAccess.Read(
|
|
cachedFile.Handle,
|
|
buffer.AsSpan(0, request),
|
|
unchecked((long)absoluteOffset));
|
|
|
|
if (read <= 0)
|
|
{
|
|
break;
|
|
}
|
|
|
|
if (!ctx.Memory.TryWrite(destination + bytesRead, buffer.AsSpan(0, read)))
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_MEMORY_FAULT;
|
|
}
|
|
|
|
bytesRead += (ulong)read;
|
|
}
|
|
}
|
|
catch (UnauthorizedAccessException)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_PERMISSION_DENIED;
|
|
}
|
|
catch (IOException)
|
|
{
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_ERROR_NOT_FOUND;
|
|
}
|
|
finally
|
|
{
|
|
ArrayPool<byte>.Shared.Return(buffer);
|
|
}
|
|
|
|
return (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
}
|
|
|
|
private static bool TryGetCachedHostFile(string hostPath, out CachedHostFile file, out int result)
|
|
{
|
|
file = null!;
|
|
result = (int)OrbisGen2Result.ORBIS_GEN2_OK;
|
|
|
|
string cachePath;
|
|
try
|
|
{
|
|
cachePath = Path.GetFullPath(hostPath);
|
|
}
|
|
catch
|
|
{
|
|
cachePath = hostPath;
|
|
}
|
|
|
|
var lazy = _hostFileCache.GetOrAdd(
|
|
cachePath,
|
|
static path => new Lazy<CachedHostFile>(() => new CachedHostFile(path), isThreadSafe: true));
|
|
|
|
try
|
|
{
|
|
file = lazy.Value;
|
|
return true;
|
|
}
|
|
catch (UnauthorizedAccessException)
|
|
{
|
|
_hostFileCache.TryRemove(cachePath, out _);
|
|
result = (int)OrbisGen2Result.ORBIS_GEN2_ERROR_PERMISSION_DENIED;
|
|
return false;
|
|
}
|
|
catch (IOException)
|
|
{
|
|
_hostFileCache.TryRemove(cachePath, out _);
|
|
result = (int)OrbisGen2Result.ORBIS_GEN2_ERROR_NOT_FOUND;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
private static bool AppendReadFileRecord(
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CpuContext ctx,
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ulong commandBuffer,
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uint fileId,
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ulong destination,
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ulong size,
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ulong fileOffset,
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ulong bytesRead)
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{
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Span<byte> record = stackalloc byte[(int)ReadFileRecordSize];
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record.Clear();
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BinaryPrimitives.WriteUInt32LittleEndian(record[0x00..], ReadFileRecordType);
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BinaryPrimitives.WriteUInt32LittleEndian(record[0x04..], fileId);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x08..], destination);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x10..], size);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x18..], fileOffset);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x20..], bytesRead);
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return AppendCommandBufferRecord(ctx, commandBuffer, record);
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}
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private static bool AppendKernelEventQueueRecord(
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CpuContext ctx,
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ulong commandBuffer,
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ulong equeue,
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ulong ident,
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ulong completionToken,
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ulong userData)
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{
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Span<byte> record = stackalloc byte[(int)KernelEventQueueRecordSize];
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record.Clear();
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BinaryPrimitives.WriteUInt32LittleEndian(record[0x00..], KernelEventQueueRecordType);
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BinaryPrimitives.WriteInt16LittleEndian(record[0x04..], KernelEventQueueCompatExports.KernelEventFilterAmpr);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x08..], equeue);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x10..], ident);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x18..], userData);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x20..], completionToken);
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return AppendCommandBufferRecord(ctx, commandBuffer, record);
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}
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|
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private static bool AppendWriteAddressRecord(CpuContext ctx, ulong commandBuffer, ulong address, ulong value)
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{
|
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Span<byte> record = stackalloc byte[(int)WriteAddressRecordSize];
|
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record.Clear();
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BinaryPrimitives.WriteUInt32LittleEndian(record[0x00..], WriteAddressRecordType);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x08..], address);
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BinaryPrimitives.WriteUInt64LittleEndian(record[0x10..], value);
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|
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return AppendCommandBufferRecord(ctx, commandBuffer, record);
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}
|
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|
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private static bool AppendCommandBufferRecord(CpuContext ctx, ulong commandBuffer, ReadOnlySpan<byte> record)
|
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{
|
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if (!TryGetCommandBufferState(ctx, commandBuffer, out _, out _, out var state) || state is null)
|
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{
|
|
return false;
|
|
}
|
|
|
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var recordSize = (ulong)record.Length;
|
|
lock (state)
|
|
{
|
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if (state.Buffer == 0 ||
|
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state.WriteOffset > state.Size ||
|
|
recordSize > state.Size - state.WriteOffset)
|
|
{
|
|
return false;
|
|
}
|
|
|
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if (!ctx.Memory.TryWrite(state.Buffer + state.WriteOffset, record))
|
|
{
|
|
return false;
|
|
}
|
|
|
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state.WriteOffset += recordSize;
|
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state.CommandCount++;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
private static bool CompleteKernelEventQueueRecord(CpuContext ctx, ulong recordAddress)
|
|
{
|
|
Span<byte> record = stackalloc byte[(int)KernelEventQueueRecordSize];
|
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if (!ctx.Memory.TryRead(recordAddress, record))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
var filter = unchecked((short)BinaryPrimitives.ReadUInt32LittleEndian(record[0x04..]));
|
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var equeue = BinaryPrimitives.ReadUInt64LittleEndian(record[0x08..]);
|
|
var ident = BinaryPrimitives.ReadUInt64LittleEndian(record[0x10..]);
|
|
var userData = BinaryPrimitives.ReadUInt64LittleEndian(record[0x18..]);
|
|
var data = BinaryPrimitives.ReadUInt64LittleEndian(record[0x20..]);
|
|
var extra = BinaryPrimitives.ReadUInt64LittleEndian(record[0x28..]);
|
|
|
|
var queuedEvent = new KernelEventQueueCompatExports.KernelQueuedEvent(
|
|
ident,
|
|
filter,
|
|
0x20,
|
|
unchecked((uint)extra),
|
|
data,
|
|
userData);
|
|
|
|
_ = KernelEventQueueCompatExports.EnqueueEvent(equeue, queuedEvent);
|
|
TraceAmpr(ctx, "complete_equeue", equeue, ident, data);
|
|
return true;
|
|
}
|
|
|
|
private static bool CompleteWriteAddressRecord(CpuContext ctx, ulong recordAddress)
|
|
{
|
|
Span<byte> record = stackalloc byte[(int)WriteAddressRecordSize];
|
|
if (!ctx.Memory.TryRead(recordAddress, record))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
var address = BinaryPrimitives.ReadUInt64LittleEndian(record[0x08..]);
|
|
var value = BinaryPrimitives.ReadUInt64LittleEndian(record[0x10..]);
|
|
if (!ctx.TryWriteUInt64(address, value))
|
|
{
|
|
return false;
|
|
}
|
|
|
|
TraceAmpr(ctx, "complete_write_address", address, value, 0);
|
|
return true;
|
|
}
|
|
|
|
private static bool TryReadUInt32(CpuContext ctx, ulong address, out uint value)
|
|
{
|
|
Span<byte> buffer = stackalloc byte[sizeof(uint)];
|
|
if (!ctx.Memory.TryRead(address, buffer))
|
|
{
|
|
value = 0;
|
|
return false;
|
|
}
|
|
|
|
value = BinaryPrimitives.ReadUInt32LittleEndian(buffer);
|
|
return true;
|
|
}
|
|
|
|
private static void TraceAmpr(CpuContext ctx, string operation, ulong commandBuffer, ulong arg0, ulong arg1)
|
|
{
|
|
if (!_traceAmpr)
|
|
{
|
|
return;
|
|
}
|
|
|
|
var returnRip = 0UL;
|
|
_ = ctx.TryReadUInt64(ctx[CpuRegister.Rsp], out returnRip);
|
|
Console.Error.WriteLine(
|
|
$"[LOADER][TRACE] ampr.{operation}: cmd=0x{commandBuffer:X16} arg0=0x{arg0:X16} arg1=0x{arg1:X16} ret=0x{returnRip:X16}");
|
|
}
|
|
|
|
private static void TraceAmprRead(
|
|
CpuContext ctx,
|
|
ulong commandBuffer,
|
|
uint fileId,
|
|
ulong destination,
|
|
ulong size,
|
|
ulong fileOffset,
|
|
ulong bytesRead,
|
|
string? hostPath,
|
|
int result)
|
|
{
|
|
if (!_traceAmprReads)
|
|
{
|
|
return;
|
|
}
|
|
|
|
var returnRip = 0UL;
|
|
_ = ctx.TryReadUInt64(ctx[CpuRegister.Rsp], out returnRip);
|
|
Console.Error.WriteLine(
|
|
$"[LOADER][TRACE] ampr.read_file: cmd=0x{commandBuffer:X16} id=0x{fileId:X8} dst=0x{destination:X16} size=0x{size:X16} offset=0x{fileOffset:X16} read=0x{bytesRead:X16} result=0x{result:X8} path='{hostPath ?? string.Empty}' ret=0x{returnRip:X16}");
|
|
}
|
|
}
|