mirror of
https://github.com/par274/sharpemu.git
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fix(gta): restore wiped GTA foundation and gameplay path (PPSA04264) (#650)
* fix(kernel): implement APR ResolveFilepathsWithPrefixToIdsAndFileSizes Resource streamers resolve relative paths against a shared prefix; without this HLE every call returned NOT_FOUND and assets never got real ids/sizes. * fix(remoteplay): stub Initialize and GetConnectionStatus as disconnected Titles probe Remote Play during pad/network bring-up; unresolved imports returned NOT_FOUND. Report initialized + disconnected so callers take the normal offline path. * fix(agc): accept Gen5 hull shaders that omit PGM_LO/HI in CreateShader Type-5 headers can start with RSRC1/RSRC2; rejecting them left null handles and Main Thread AVs. Scan the SH table and skip PGM patch when absent. Co-authored-by: Cursor <cursoragent@cursor.com> * fix(kernel): reject getdents on file fds and emit . / .. for empty dirs Returning rax=0 for non-directory or empty listings looked like EOF and let GTA treat the fd as a pointer (fiWriteAsyncDataWorker AV at 0xB1). * fix(hle): enable GuestImageWriteTracker CPU sync on Windows Windows previously hard-disabled the tracker, so CPU-written guest planes never marked dirty and host textures stayed empty. Arm pages with VirtualProtect, handle write AVs in VEH, and warm/test on VirtualAlloc memory so protect cannot poison the CRT heap. * fix(agc): skip CB metadata draws for EliminateFastClear/Fmask/DCC CB_COLOR_CONTROL modes 2/5/6 are colour-buffer metadata ops; applying the bound shader as a normal colour draw corrupts subsequent composites. Decode MODE from bits [6:4] and return before translate. * fix(agc): merge Prospero attrib-table formats onto IR vertex inputs IR-discovered BufferLoadFormat often keeps a stale float sharp format; patch DataFormat/offset from the AGC attrib table (semantic index), allow offen fetches, and map quirks 113/121 through NarrowVk for host vertex input. * fix(audio): harden AudioOut2 stack out-buffer writes against canary smash Titles that stack-allocate AudioOut2 outs next to the frame canary were corrupted by oversized or mistyped HLE writes; keep ContextPush pacing. * Revert "fix(memory): reserve only large regions (#608)" This reverts commit8f9456229a. * fix(gpu): decode Gen5 R16 and RG32 render-target formats * fix(audio): AudioOut2 host beds, deeper waveOut queue, AJM MP3 GTA V Enhanced routes intro/menu audio through AudioOut2 and FMOD's AJM MP3 path. Wire PortCreate/PortSetAttributes/ContextPush to dual host stereo streams, deepen WinMM queue to 128KiB, and decode AJM codec 0 with a stateful NLayer helper so menu music is not silent. * fix(agc): map PS interpolants via SPI_PS_INPUT_CNTL semantics Identity ATTR→param wiring ignored hardware remapping, so UI draws got wrong (or empty) interpolants. Pack CNTL from matched PS/GS semantics, thread it into Vulkan/Metal as Location/Flat, and fingerprint it in the graphics shader cache key. * fix(agc): rect-list/NGG strips, Index8 expand, and GE_INDX_OFFSET NGG single-rect UI needs triangle-strip expansion; Prospero Index8 must expand to host u16; glyphs need base vertex from GE_INDX_OFFSET. Skip param-less rect-lists instead of inventing colour draws. * fix(np): report GTA Story Mode addcont entitlements as owned NpEntitlementAccess was returning an empty add-on list, so GTA V Enhanced offered Buy Story Mode. Publish the installed license labels and stub premium-event registration so offline sessions take the owned path. * fix(cpu): prefer native workers for all guest entry stubs Route thread entry, continuation, and main entry through RunGuestEntryStub so guest stubs are not invoked above CLR-managed frames (UnmanagedCallersOnly FailFast). Keep requireNativeWorker for tbb_thead; other paths prefer workers with calli fallback. * fix(agc): implement Rewind/Jump writers and IT_REWIND waits GTA Subrender AVs came from AcbJumpGetSize / DcbRewind returning NOT_FOUND as packet sizes. Add IT_REWIND and INDIRECT_BUFFER writers, patch SetRewindState into the GPU wait registry, and nest-parse 4-dword jumps. * fix(gpu): use AddrLib ExactXor for Gen5 Standard256B (mode 1) Mode 5 already had Standard4K ExactXor; mode 1 still used the generic StandardSwizzle block table, which mis-detiles Gen5 UI atlases. * Revert "fix(cpu): prefer native workers for all guest entry stubs" This reverts commit31c4db0d38. * fix(memory): commit-first large maps; reserve only on failure Replace the #608 always-reserve-only exact-map path with allocate-first and lazy reserve fallback when a huge non-exec commit cannot be satisfied. Prime and widen GetPointer commit so the fallback path is safer for native walkers. Drops the need for a hard #608 revert. * [Agc] Implement fused shader half exports * fix(agc): accept optional hull state in CreatePrimState Port the CreatePrimState hull-optional path from #583 so fused HS pipelines (GTA) are not rejected with INVALID_ARGUMENT. Geometry-derived CX/UC writes are unchanged; hull is traced only. * fix(videoout): restore thread-safe VulkanHostBufferPool (#564) The6db095ewipe dropped CasualcoderDev's lock-ordering-safe pool. Concurrent Return/TryTake without the gate races after the first present and can hang the submit path. * Revert "fix(agc): implement Rewind/Jump writers and IT_REWIND waits" This reverts commitbec77bf083. * test(memory): align lazy-commit expectations with commit-first policy Fake hosts must reject Allocate so reserve-only paths still run, and GetPointer asserts the 32 MiB prime range including AlignUp spill. * diag(gpu): log guest-queue backlog breakdown under backpressure Rate-limit top work types and ordered debugName prefixes when the Vulkan guest work queue stalls, so North Yankton logs show acquire/label vs draw traffic instead of only VulkanOrderedGuestAction. * perf(agc): coalesce acquire flushes and batch non-DMA label wakes Flush pending ACQUIRE_MEM invalidation at draw/dispatch/dma/flip boundaries instead of before every packet, and complete release/write-data producers in the same ordered action so load paths enqueue far fewer VulkanOrderedGuestAction items. * perf(gpu): wait for ordered-action fences and keep draining sync On Windows/Linux, block briefly for queue-visibility fences instead of deferring the whole logical queue for the tick. Prefer ordered sync/flip heads under backlog pressure, and keep macOS non-blocking defer behavior. * perf(gpu): raise sync-item ceiling above payload guest-work cap Apply SHARPEMU_PENDING_GUEST_WORK_ITEMS mainly to compute/draw/image payload work, and allow a higher SHARPEMU_PENDING_GUEST_SYNC_ITEMS ceiling for zero-payload ordered actions and flip markers. Keep the byte budget as the RAM safety valve. * fix(gta): stub Voice ports and implement sceKernelCheckReachability Resolve North Yankton-path Voice Create/Delete/Connect/Disconnect/End NIDs and EnumerationThread reachability checks so leftover unresolved imports are not on the critical path. * diag(gta): arm flip/present/wait probes after North Audio Rate-limited load_progress TRACE for flip submit, ordered flip enqueue, present taken/not-taken, and GPU wait backlog so North Yankton freezes can be classified without full AGC tracing. * fix(ampr): restore sequential offset=-1 reads for streamer packs Re-wire PakDirectoryTracker into sceAmprAprCommandBufferReadFile (dropped in #216) so RAGE sequential pack reads no longer fail while the North Yankton UI keeps flipping. Also rate-limit CheckReachability miss paths for EnumerationThread diagnosis. * fix(hle/videoout): Windows GuestImage opt-in and keep GTA intro without sync Default the tracker off on Windows to avoid VirtualProtect thrash, gate AGC texel-copy skips on Enabled so guest Bink planes keep shipping pixels, and drain CPU-written images on the present thread when sync is opted in. * fix(videoout): probe guest content when tracker off so UI can skip copies Restores upload-known/texture-cache skips for Dead Cells menus, and uses a sparse guest-memory fingerprint when GuestImageWriteTracker is disabled so CPU-updated Bink planes still force texel copies for GTA intro. * fix(audio): keep 128KiB host queue AudioOut2-only Restore the default 32 KiB (~171 ms) PCM bed for classic AudioOut so titles like Dreaming Sarah stay in sync; only AudioOut2 opens the deeper queue needed for bursty FMOD Push on GTA. --------- Co-authored-by: samto6 <123419830+samto6@users.noreply.github.com>
This commit is contained in:
MarcelMediaDev
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Agc;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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// sceAgcGetFusedShaderSize (dolOmWH+huQ) and sceAgcFuseShaderHalves (fd5Bp5tGTgo)
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// join a GS or HS front/back shader half pair into one shader: the fused header
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// is the back half retyped, the back half's SH registers become the fused
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// register image, and the front half contributes its program address
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// (SPI_SHADER_PGM_LO/HI_ES) and checksum registers.
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public sealed class AgcFusedShaderTests
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{
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private const ulong BaseAddress = 0x1_0000_0000;
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private const int MemorySize = 0x4000;
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private const ulong FrontShader = BaseAddress + 0x0000;
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private const ulong BackShader = BaseAddress + 0x0100;
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private const ulong FusedShader = BaseAddress + 0x0200;
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private const ulong FrontRegisters = BaseAddress + 0x0300;
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private const ulong BackRegisters = BaseAddress + 0x0400;
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private const ulong FrontSpecials = BaseAddress + 0x0500;
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private const ulong BackSpecials = BaseAddress + 0x0600;
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private const ulong Scratch = BaseAddress + 0x0700;
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private const ulong SizeResult = BaseAddress + 0x0800;
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private const ulong ShaderUserDataOffset = 0x08;
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private const ulong ShaderCodeOffset = 0x10;
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private const ulong ShaderShRegistersOffset = 0x20;
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private const ulong ShaderSpecialsOffset = 0x28;
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private const ulong ShaderTypeOffset = 0x5A;
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private const ulong ShaderNumShRegistersOffset = 0x5C;
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private const byte GsFront = 4;
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private const byte HsFront = 5;
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private const byte GsBack = 6;
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private const byte HsBack = 7;
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private const ulong FrontCode = 0x0000_1234_5678_9A00;
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[Fact]
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public void GetFusedShaderSize_GsPair_ReportsBackRegisterBytes()
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{
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var (memory, ctx) = CreateGsPair();
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ctx[CpuRegister.Rdi] = SizeResult;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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var result = AgcExports.GetFusedShaderSize(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(5UL * 8UL, ReadUInt64(memory, SizeResult));
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Assert.Equal(4UL, ReadUInt64(memory, SizeResult + 8));
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}
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[Fact]
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public void GetFusedShaderSize_MismatchedHalves_Rejects()
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{
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var (memory, ctx) = CreateGsPair();
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WriteByte(memory, BackShader + ShaderTypeOffset, HsBack);
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ctx[CpuRegister.Rdi] = SizeResult;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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var result = AgcExports.GetFusedShaderSize(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT, result);
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Assert.Equal(0UL, ReadUInt64(memory, SizeResult));
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}
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[Fact]
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public void FuseShaderHalves_GsPairWithScratch_BuildsFusedShader()
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{
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var (memory, ctx) = CreateGsPair();
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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// Fused header is the back half with type kGs, cleared user data, and
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// registers relocated to the scratch image.
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Assert.Equal(2, ReadByte(memory, FusedShader + ShaderTypeOffset));
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Assert.Equal(0UL, ReadUInt64(memory, FusedShader + ShaderUserDataOffset));
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Assert.Equal(Scratch, ReadUInt64(memory, FusedShader + ShaderShRegistersOffset));
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Assert.Equal(5, ReadByte(memory, FusedShader + ShaderNumShRegistersOffset));
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Assert.Equal(
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ReadUInt64(memory, BackShader + ShaderCodeOffset),
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ReadUInt64(memory, FusedShader + ShaderCodeOffset));
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// The back half's own register image is untouched.
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Assert.Equal(0x1111_1111u, ReadUInt32(memory, BackRegisters + 4));
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// Scratch image: LO_ES points at the front code, HI_ES keeps its upper
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// bits, both checksum occurrences carry the front half's values.
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Assert.Equal(0xC8u, ReadUInt32(memory, Scratch + 0));
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Assert.Equal(0x3456_789Au, ReadUInt32(memory, Scratch + 4));
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Assert.Equal(0xC9u, ReadUInt32(memory, Scratch + 8));
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Assert.Equal(0xAABB_CC12u, ReadUInt32(memory, Scratch + 12));
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Assert.Equal(0xAAAA_0001u, ReadUInt32(memory, Scratch + 20));
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Assert.Equal(0xBBBB_0002u, ReadUInt32(memory, Scratch + 28));
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Assert.Equal(0x5555_5555u, ReadUInt32(memory, Scratch + 36));
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}
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[Fact]
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public void FuseShaderHalves_NoScratch_PatchesBackRegistersInPlace()
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{
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var (memory, ctx) = CreateGsPair();
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = 0;
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var result = AgcExports.FuseShaderHalves(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(BackRegisters, ReadUInt64(memory, FusedShader + ShaderShRegistersOffset));
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Assert.Equal(0x3456_789Au, ReadUInt32(memory, BackRegisters + 4));
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Assert.Equal(0xAABB_CC12u, ReadUInt32(memory, BackRegisters + 12));
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}
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[Fact]
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public void FuseShaderHalves_WaveSizeMismatch_Rejects()
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{
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var (memory, ctx) = CreateGsPair();
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WriteUInt32(memory, BackSpecials + 0x08 + 4, 0u);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_ERROR_INVALID_ARGUMENT, result);
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Assert.Equal(0, ReadByte(memory, FusedShader + ShaderTypeOffset));
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}
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[Fact]
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public void FuseShaderHalves_HsPair_PatchesLoLs()
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{
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var (memory, ctx) = CreateGsPair();
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WriteByte(memory, FrontShader + ShaderTypeOffset, HsFront);
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WriteByte(memory, BackShader + ShaderTypeOffset, HsBack);
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WriteUInt32(memory, BackRegisters + 0, 0x148u);
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WriteUInt32(memory, BackRegisters + 8, 0x149u);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(3, ReadByte(memory, FusedShader + ShaderTypeOffset));
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Assert.Equal(0x3456_789Au, ReadUInt32(memory, Scratch + 4));
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// Checksum grafting is a geometry-pair behavior; the HS image keeps its own values.
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Assert.Equal(0x1111_0001u, ReadUInt32(memory, Scratch + 20));
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}
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[Fact]
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public void FuseShaderHalves_MissingSpecials_SkipsWaveSizeGate()
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{
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var (memory, ctx) = CreateGsPair();
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// The divergence the mismatch test rejects passes when a half lacks specials.
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WriteUInt64(memory, FrontShader + ShaderSpecialsOffset, 0);
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WriteUInt32(memory, BackSpecials + 0x08 + 4, 0u);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(2, ReadByte(memory, FusedShader + ShaderTypeOffset));
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}
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[Fact]
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public void FuseShaderHalves_ProgramRegisterAbsent_LeavesImageUntouched()
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{
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var (memory, ctx) = CreateGsPair();
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WriteByte(memory, FrontShader + ShaderTypeOffset, HsFront);
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WriteByte(memory, BackShader + ShaderTypeOffset, HsBack);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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// No LO_LS entry in the back image: the fuse still succeeds and the
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// scratch copy stays verbatim.
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(3, ReadByte(memory, FusedShader + ShaderTypeOffset));
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Assert.Equal(0x1111_1111u, ReadUInt32(memory, Scratch + 4));
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Assert.Equal(0xAABB_CC77u, ReadUInt32(memory, Scratch + 12));
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}
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[Fact]
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public void FuseShaderHalves_UnpairedProgramRegister_LeavesImageUntouched()
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{
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var (memory, ctx) = CreateGsPair();
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WriteByte(memory, FrontShader + ShaderTypeOffset, HsFront);
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WriteByte(memory, BackShader + ShaderTypeOffset, HsBack);
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WriteUInt32(memory, BackRegisters + 0, 0x148u);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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// LO_LS is present but the next entry is not HI_LS, so the patch is skipped.
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(0x1111_1111u, ReadUInt32(memory, Scratch + 4));
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}
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[Fact]
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public void FuseShaderHalves_ProgramRegisterAtImageEnd_LeavesImageUntouched()
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{
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var (memory, ctx) = CreateGsPair();
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WriteByte(memory, FrontShader + ShaderTypeOffset, HsFront);
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WriteByte(memory, BackShader + ShaderTypeOffset, HsBack);
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WriteUInt32(memory, BackRegisters + 4 * 8, 0x148u);
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ctx[CpuRegister.Rdi] = FusedShader;
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ctx[CpuRegister.Rsi] = FrontShader;
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ctx[CpuRegister.Rdx] = BackShader;
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ctx[CpuRegister.Rcx] = Scratch;
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var result = AgcExports.FuseShaderHalves(ctx);
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// The hi half of the pair would sit past the register image.
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Assert.Equal((int)OrbisGen2Result.ORBIS_GEN2_OK, result);
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Assert.Equal(0x5555_5555u, ReadUInt32(memory, Scratch + 36));
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}
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private static (FakeCpuMemory Memory, CpuContext Ctx) CreateGsPair()
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{
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var memory = new FakeCpuMemory(BaseAddress, MemorySize);
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var ctx = new CpuContext(memory, Generation.Gen5);
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WriteByte(memory, FrontShader + ShaderTypeOffset, GsFront);
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WriteUInt64(memory, FrontShader + ShaderCodeOffset, FrontCode);
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WriteUInt64(memory, FrontShader + ShaderShRegistersOffset, FrontRegisters);
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WriteUInt64(memory, FrontShader + ShaderSpecialsOffset, FrontSpecials);
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WriteByte(memory, FrontShader + ShaderNumShRegistersOffset, 4);
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WriteByte(memory, BackShader + ShaderTypeOffset, GsBack);
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WriteUInt64(memory, BackShader + ShaderCodeOffset, 0x0000_0BAD_F00D_BE00);
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WriteUInt64(memory, BackShader + ShaderShRegistersOffset, BackRegisters);
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WriteUInt64(memory, BackShader + ShaderSpecialsOffset, BackSpecials);
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WriteUInt64(memory, BackShader + ShaderUserDataOffset, 0xDEAD_BEEF);
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WriteByte(memory, BackShader + ShaderNumShRegistersOffset, 5);
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// Back image: ES program address pair, two checksum slots, one bystander.
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WriteRegister(memory, BackRegisters, 0, 0xC8u, 0x1111_1111u);
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WriteRegister(memory, BackRegisters, 1, 0xC9u, 0xAABB_CC77u);
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WriteRegister(memory, BackRegisters, 2, 0x80u, 0x1111_0001u);
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WriteRegister(memory, BackRegisters, 3, 0x80u, 0x1111_0002u);
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WriteRegister(memory, BackRegisters, 4, 0x10u, 0x5555_5555u);
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// Front image: GS RSRC pair as shipped, then the checksum values to graft.
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WriteRegister(memory, FrontRegisters, 0, 0x8Au, 0x0123_4567u);
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WriteRegister(memory, FrontRegisters, 1, 0x8Bu, 0x89AB_CDEFu);
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WriteRegister(memory, FrontRegisters, 2, 0x80u, 0xAAAA_0001u);
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WriteRegister(memory, FrontRegisters, 3, 0x80u, 0xBBBB_0002u);
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// VGT_SHADER_STAGES_EN register pairs with the GS wave32 enable bit set on both halves.
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WriteUInt32(memory, FrontSpecials + 0x08, 0x1F1u);
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WriteUInt32(memory, FrontSpecials + 0x08 + 4, 1u << 22);
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WriteUInt32(memory, BackSpecials + 0x08, 0x1F1u);
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WriteUInt32(memory, BackSpecials + 0x08 + 4, 1u << 22);
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return (memory, ctx);
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}
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private static void WriteRegister(FakeCpuMemory memory, ulong array, int index, uint offset, uint value)
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{
|
||||
WriteUInt32(memory, array + (ulong)index * 8, offset);
|
||||
WriteUInt32(memory, array + (ulong)index * 8 + 4, value);
|
||||
}
|
||||
|
||||
private static void WriteByte(FakeCpuMemory memory, ulong address, byte value)
|
||||
{
|
||||
Span<byte> buffer = [value];
|
||||
Assert.True(memory.TryWrite(address, buffer));
|
||||
}
|
||||
|
||||
private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(uint)];
|
||||
BinaryPrimitives.WriteUInt32LittleEndian(buffer, value);
|
||||
Assert.True(memory.TryWrite(address, buffer));
|
||||
}
|
||||
|
||||
private static void WriteUInt64(FakeCpuMemory memory, ulong address, ulong value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(ulong)];
|
||||
BinaryPrimitives.WriteUInt64LittleEndian(buffer, value);
|
||||
Assert.True(memory.TryWrite(address, buffer));
|
||||
}
|
||||
|
||||
private static byte ReadByte(FakeCpuMemory memory, ulong address)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[1];
|
||||
Assert.True(memory.TryRead(address, buffer));
|
||||
return buffer[0];
|
||||
}
|
||||
|
||||
private static uint ReadUInt32(FakeCpuMemory memory, ulong address)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(uint)];
|
||||
Assert.True(memory.TryRead(address, buffer));
|
||||
return BinaryPrimitives.ReadUInt32LittleEndian(buffer);
|
||||
}
|
||||
|
||||
private static ulong ReadUInt64(FakeCpuMemory memory, ulong address)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[sizeof(ulong)];
|
||||
Assert.True(memory.TryRead(address, buffer));
|
||||
return BinaryPrimitives.ReadUInt64LittleEndian(buffer);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,66 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Buffers.Binary;
|
||||
using SharpEmu.HLE;
|
||||
using SharpEmu.Libs.Agc;
|
||||
using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests.Agc;
|
||||
|
||||
public sealed class AgcPrimStateHullVariantTests
|
||||
{
|
||||
private const ulong BaseAddress = 0x1_0000_0000;
|
||||
private const ulong CxRegistersAddress = BaseAddress + 0x100;
|
||||
private const ulong UcRegistersAddress = BaseAddress + 0x200;
|
||||
private const ulong HullStateAddress = BaseAddress + 0x300;
|
||||
private const ulong GeometryShaderAddress = BaseAddress + 0x400;
|
||||
private const ulong SpecialsAddress = BaseAddress + 0x500;
|
||||
|
||||
// Tessellation pipelines pass a non-null hull-state block; the
|
||||
// geometry-derived register writes must still happen instead of an
|
||||
// INVALID_ARGUMENT that leaves the caller's register storage as garbage.
|
||||
[Fact]
|
||||
public void CreatePrimState_AcceptsHullStateBlock()
|
||||
{
|
||||
var memory = new FakeCpuMemory(BaseAddress, 0x1000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
memory.TryWrite(GeometryShaderAddress + 0x5A, new byte[] { 2 });
|
||||
WriteUInt64(memory, GeometryShaderAddress + 0x28, SpecialsAddress);
|
||||
|
||||
// Specials: {register, value} pairs at GeCntl 0x00, StagesEn 0x08,
|
||||
// GsOutPrimType 0x20, GeUserVgprEn 0x28.
|
||||
WriteUInt64(memory, SpecialsAddress + 0x00, 0x0000_0111_0000_0222UL);
|
||||
WriteUInt64(memory, SpecialsAddress + 0x08, 0x0000_0333_0000_0444UL);
|
||||
WriteUInt64(memory, SpecialsAddress + 0x20, 0x0000_0555_0000_0666UL);
|
||||
WriteUInt64(memory, SpecialsAddress + 0x28, 0x0000_0777_0000_0888UL);
|
||||
|
||||
ctx[CpuRegister.Rdi] = CxRegistersAddress;
|
||||
ctx[CpuRegister.Rsi] = UcRegistersAddress;
|
||||
ctx[CpuRegister.Rdx] = HullStateAddress;
|
||||
ctx[CpuRegister.Rcx] = GeometryShaderAddress;
|
||||
ctx[CpuRegister.R8] = 0x11;
|
||||
|
||||
Assert.Equal(
|
||||
(int)OrbisGen2Result.ORBIS_GEN2_OK,
|
||||
AgcExports.CreatePrimState(ctx));
|
||||
|
||||
Assert.NotEqual(0u, ReadUInt32(memory, CxRegistersAddress));
|
||||
Assert.Equal(0x11u, ReadUInt32(memory, UcRegistersAddress + 20));
|
||||
}
|
||||
|
||||
private static void WriteUInt64(FakeCpuMemory memory, ulong address, ulong value)
|
||||
{
|
||||
Span<byte> bytes = stackalloc byte[sizeof(ulong)];
|
||||
BinaryPrimitives.WriteUInt64LittleEndian(bytes, value);
|
||||
Assert.True(memory.TryWrite(address, bytes));
|
||||
}
|
||||
|
||||
private static uint ReadUInt32(FakeCpuMemory memory, ulong address)
|
||||
{
|
||||
Span<byte> value = stackalloc byte[sizeof(uint)];
|
||||
Assert.True(memory.TryRead(address, value));
|
||||
return BinaryPrimitives.ReadUInt32LittleEndian(value);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,95 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Buffers.Binary;
|
||||
using SharpEmu.Libs.Agc;
|
||||
using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests.Agc;
|
||||
|
||||
/// <summary>
|
||||
/// Regression coverage for the AGC UI path: index8 expansion and rect-list
|
||||
/// vertex counts / topology selection.
|
||||
/// </summary>
|
||||
public sealed class AgcRectListIndexHelpersTests
|
||||
{
|
||||
[Theory]
|
||||
[InlineData(0u, 0u, 2)] // Index16
|
||||
[InlineData(1u, 1u, 4)] // Index32
|
||||
[InlineData(2u, 2u, 1)] // Index8
|
||||
[InlineData(0x402u, 2u, 1)] // UC 0x400|size -> Index8
|
||||
public void IndexType_DecodeAndStride_MatchProspero(uint raw, uint expected, int stride)
|
||||
{
|
||||
var decoded = AgcIndexHelpers.Decode(raw);
|
||||
Assert.Equal((AgcIndexHelpers.ProsperoIndexType)expected, decoded);
|
||||
Assert.Equal(stride, AgcIndexHelpers.GetGuestStrideBytes(decoded));
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void ExpandIndex8ToU16_PreservesValues()
|
||||
{
|
||||
ReadOnlySpan<byte> source = [0x00, 0x01, 0xFF, 0x7F];
|
||||
Span<byte> destination = stackalloc byte[8];
|
||||
AgcIndexHelpers.ExpandIndex8ToU16(source, destination);
|
||||
Assert.Equal(0, BinaryPrimitives.ReadUInt16LittleEndian(destination[..2]));
|
||||
Assert.Equal(1, BinaryPrimitives.ReadUInt16LittleEndian(destination.Slice(2, 2)));
|
||||
Assert.Equal(255, BinaryPrimitives.ReadUInt16LittleEndian(destination.Slice(4, 2)));
|
||||
Assert.Equal(127, BinaryPrimitives.ReadUInt16LittleEndian(destination.Slice(6, 2)));
|
||||
}
|
||||
|
||||
[Theory]
|
||||
// NGG single-rect UI (DualSense): expand even when VBs are present
|
||||
[InlineData(7u, 3u, false, true, 4u)]
|
||||
[InlineData(7u, 1u, false, false, 4u)]
|
||||
[InlineData(7u, 4u, false, true, 4u)]
|
||||
// Indexed / multi-vert auto: keep guest count (loading video)
|
||||
[InlineData(7u, 3u, true, false, 3u)]
|
||||
[InlineData(7u, 6u, false, true, 6u)]
|
||||
[InlineData(7u, 4u, true, true, 4u)]
|
||||
[InlineData(0x11u, 3u, false, false, 4u)]
|
||||
[InlineData(0x11u, 6u, false, false, 6u)]
|
||||
[InlineData(4u, 3u, false, false, 3u)]
|
||||
public void RectListDrawVertexCount_MatchesExpansion(
|
||||
uint primitiveType,
|
||||
uint vertexCount,
|
||||
bool indexed,
|
||||
bool hasVertexBuffers,
|
||||
uint expected)
|
||||
{
|
||||
Assert.Equal(
|
||||
expected,
|
||||
AgcPrimitiveHelpers.GetRectListDrawVertexCount(
|
||||
primitiveType,
|
||||
vertexCount,
|
||||
indexed,
|
||||
hasVertexBuffers));
|
||||
}
|
||||
|
||||
[Theory]
|
||||
[InlineData(7u, false, 3u, true, true)]
|
||||
[InlineData(7u, false, 6u, true, false)]
|
||||
[InlineData(7u, true, 3u, false, false)]
|
||||
[InlineData(0x11u, false, 3u, true, true)]
|
||||
[InlineData(0x11u, true, 3u, false, false)]
|
||||
public void RectListTriangleStrip_MatchesGuards(
|
||||
uint primitiveType,
|
||||
bool indexed,
|
||||
uint vertexCount,
|
||||
bool hasVertexBuffers,
|
||||
bool expected) =>
|
||||
Assert.Equal(
|
||||
expected,
|
||||
AgcPrimitiveHelpers.ShouldDrawRectListAsTriangleStrip(
|
||||
primitiveType,
|
||||
indexed,
|
||||
vertexCount,
|
||||
hasVertexBuffers));
|
||||
|
||||
[Theory]
|
||||
[InlineData(7u, (uint)AgcPrimitiveHelpers.GsOutputPrimitiveType.Rectangle2D)]
|
||||
[InlineData(0x11u, (uint)AgcPrimitiveHelpers.GsOutputPrimitiveType.RectList)]
|
||||
[InlineData(4u, (uint)AgcPrimitiveHelpers.GsOutputPrimitiveType.Triangles)]
|
||||
[InlineData(1u, (uint)AgcPrimitiveHelpers.GsOutputPrimitiveType.Points)]
|
||||
public void PrimitiveTypeToGsOut_MatchesProspero(uint primitiveType, uint expected) =>
|
||||
Assert.Equal(expected, AgcPrimitiveHelpers.PrimitiveTypeToGsOut(primitiveType));
|
||||
}
|
||||
@@ -0,0 +1,293 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Buffers.Binary;
|
||||
using SharpEmu.HLE;
|
||||
using SharpEmu.Libs.Agc;
|
||||
using SharpEmu.ShaderCompiler;
|
||||
using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests.Agc;
|
||||
|
||||
/// <summary>
|
||||
/// Coverage for AGC attrib-table → BufferFormat merge and semantic indexing.
|
||||
/// </summary>
|
||||
public sealed class AgcVertexMetadataTests
|
||||
{
|
||||
[Fact]
|
||||
public void BuildVertexResources_UsesSemanticNotHardwareMappingAsAttribIndex()
|
||||
{
|
||||
// input_semantics[0]: semantic=1, hardware_mapping=4, size=2
|
||||
// If hardware_mapping were wrongly used as the attrib index, we'd read
|
||||
// attrib[4] instead of attrib[1] and get the wrong format/offset.
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
// ShaderSemantic word: semantic=1, hw_mapping=4, size_in_elements=2
|
||||
WriteUInt32(memory, semanticsAddress, 1u | (4u << 8) | (2u << 16));
|
||||
|
||||
// attrib[0] unused garbage
|
||||
WriteUInt32(memory, attribTable, 0xDEAD_BEEFu);
|
||||
// attrib[1]: buffer=0, format=k16_16Float(29), offset=8, fetch=0
|
||||
WriteUInt32(memory, attribTable + 4, 0u | (29u << 5) | (8u << 14));
|
||||
|
||||
// V# at buffer table[0]: base=sharpBase, stride=16
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(
|
||||
memory,
|
||||
bufferTable + 4,
|
||||
(uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[8] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[9] = (uint)(attribTable >> 32);
|
||||
scalars[10] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[11] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 10,
|
||||
VertexAttribReg: 8,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
Assert.True(
|
||||
AgcVertexMetadata.TryBuildVertexResourcesFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
out var resources));
|
||||
Assert.Single(resources);
|
||||
Assert.Equal(1u, resources[0].Semantic);
|
||||
Assert.Equal(4u, resources[0].HardwareMapping);
|
||||
Assert.Equal(8u, resources[0].OffsetBytes);
|
||||
Assert.Equal(5u, resources[0].DataFormat); // R16G16
|
||||
Assert.Equal(7u, resources[0].NumberFormat); // Float
|
||||
Assert.Equal(2u, resources[0].ComponentCount);
|
||||
Assert.Equal(sharpBase, resources[0].SharpBase);
|
||||
Assert.False(resources[0].PerInstance);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_OverlaysFormatWithoutRebasingCapture()
|
||||
{
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
// format k8_8_8_8UNorm(56), offset=12
|
||||
WriteUInt32(memory, attribTable, 0u | (56u << 5) | (12u << 14));
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
Pc: 0x40,
|
||||
Location: 0,
|
||||
ComponentCount: 4,
|
||||
DataFormat: 14, // wrong IR guess
|
||||
NumberFormat: 7,
|
||||
BaseAddress: sharpBase,
|
||||
Stride: 16,
|
||||
OffsetBytes: 0,
|
||||
Data: data,
|
||||
DataLength: data.Length,
|
||||
DataPooled: false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Single(merged);
|
||||
Assert.Equal(0u, merged[0].Location);
|
||||
Assert.Equal(sharpBase, merged[0].BaseAddress);
|
||||
Assert.Same(data, merged[0].Data);
|
||||
Assert.Equal(10u, merged[0].DataFormat); // RGBA8
|
||||
Assert.Equal(0u, merged[0].NumberFormat); // Unorm
|
||||
Assert.Equal(12u, merged[0].OffsetBytes);
|
||||
Assert.Equal(0x40u, merged[0].Pc);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_AcceptsVertexAttribFormatEnums()
|
||||
{
|
||||
// Attrib tables store VertexAttribFormat (227 = rgba8 unorm), not
|
||||
// BufferFormat (56). Without conversion the format patch is a no-op.
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, attribTable, 0u | (227u << 5) | (12u << 14)); // VertexAttribFormat
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
0x40, 0, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Equal(10u, merged[0].DataFormat);
|
||||
Assert.Equal(0u, merged[0].NumberFormat);
|
||||
Assert.Equal(12u, merged[0].OffsetBytes);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void MergeVertexInputs_MatchesInterleavedAttrsByOffsetNotBareBase()
|
||||
{
|
||||
// Both attributes share SharpBase. Matching by base alone would assign
|
||||
// the color format to position (video/UI regression).
|
||||
const ulong memoryBase = 0x1_0000_0000;
|
||||
var memory = new FakeCpuMemory(memoryBase, 0x2000);
|
||||
var ctx = new CpuContext(memory, Generation.Gen5);
|
||||
|
||||
const ulong semanticsAddress = memoryBase + 0x100;
|
||||
const ulong attribTable = memoryBase + 0x200;
|
||||
const ulong bufferTable = memoryBase + 0x300;
|
||||
const ulong sharpBase = memoryBase + 0x800;
|
||||
|
||||
// semantic0 → pos float4 @0; semantic1 → color rgba8 @12
|
||||
WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, semanticsAddress + 4, 1u | (4u << 8) | (4u << 16));
|
||||
WriteUInt32(memory, attribTable, 0u | (77u << 5) | (0u << 14)); // k32_32_32_32Float
|
||||
WriteUInt32(memory, attribTable + 4, 0u | (56u << 5) | (12u << 14)); // rgba8unorm @12
|
||||
WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
|
||||
WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
|
||||
|
||||
var scalars = new uint[32];
|
||||
scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
|
||||
scalars[5] = (uint)(attribTable >> 32);
|
||||
scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
|
||||
scalars[7] = (uint)(bufferTable >> 32);
|
||||
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 6,
|
||||
VertexAttribReg: 4,
|
||||
InputSemanticsCount: 2,
|
||||
InputSemanticsAddress: semanticsAddress);
|
||||
|
||||
var data = new byte[64];
|
||||
var discovered = new[]
|
||||
{
|
||||
new Gen5VertexInputBinding(
|
||||
0x40, 0, 4, 14, 7, sharpBase, 16, 0, data, data.Length, false),
|
||||
new Gen5VertexInputBinding(
|
||||
0x80, 1, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
|
||||
};
|
||||
|
||||
var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
|
||||
ctx,
|
||||
scalars,
|
||||
tables,
|
||||
discovered);
|
||||
Assert.Equal(2, merged.Count);
|
||||
Assert.Equal(0u, merged[0].OffsetBytes);
|
||||
Assert.Equal(12u, merged[1].OffsetBytes);
|
||||
Assert.Equal(0u, merged[1].NumberFormat); // Unorm color, not float
|
||||
Assert.Equal(10u, merged[1].DataFormat); // RGBA8
|
||||
Assert.Equal(sharpBase, merged[0].BaseAddress);
|
||||
Assert.Equal(sharpBase, merged[1].BaseAddress);
|
||||
Assert.Same(data, merged[0].Data);
|
||||
}
|
||||
|
||||
[Fact]
|
||||
public void CollectFetchPrologPcs_FindsSBufferLoadsFromTableRegisters()
|
||||
{
|
||||
var tables = new AgcVertexMetadata.VertexTableRegisters(
|
||||
VertexBufferReg: 10,
|
||||
VertexAttribReg: 8,
|
||||
InputSemanticsCount: 1,
|
||||
InputSemanticsAddress: 1);
|
||||
|
||||
var program = new Gen5ShaderProgram(
|
||||
0,
|
||||
[
|
||||
new Gen5ShaderInstruction(
|
||||
0x10,
|
||||
Gen5ShaderEncoding.Smem,
|
||||
"SBufferLoadDword",
|
||||
Words: [],
|
||||
Sources: [Gen5Operand.Scalar(8)],
|
||||
Destinations: [Gen5Operand.Scalar(20)],
|
||||
new Gen5ScalarMemoryControl(1, 0, null)),
|
||||
new Gen5ShaderInstruction(
|
||||
0x20,
|
||||
Gen5ShaderEncoding.Smem,
|
||||
"SBufferLoadDword",
|
||||
Words: [],
|
||||
Sources: [Gen5Operand.Scalar(12)],
|
||||
Destinations: [Gen5Operand.Scalar(24)],
|
||||
new Gen5ScalarMemoryControl(1, 0, null)),
|
||||
new Gen5ShaderInstruction(
|
||||
0x30,
|
||||
Gen5ShaderEncoding.Sopp,
|
||||
"SEndpgm",
|
||||
Words: [],
|
||||
Sources: [],
|
||||
Destinations: [],
|
||||
null),
|
||||
]);
|
||||
|
||||
var pcs = AgcVertexMetadata.CollectFetchPrologPcs(program, tables);
|
||||
Assert.Contains(0x10u, pcs);
|
||||
Assert.DoesNotContain(0x20u, pcs);
|
||||
}
|
||||
|
||||
private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
|
||||
{
|
||||
Span<byte> bytes = stackalloc byte[4];
|
||||
BinaryPrimitives.WriteUInt32LittleEndian(bytes, value);
|
||||
Assert.True(memory.TryWrite(address, bytes));
|
||||
}
|
||||
}
|
||||
@@ -6,7 +6,7 @@ using Xunit;
|
||||
|
||||
namespace SharpEmu.Libs.Tests.Agc;
|
||||
|
||||
// TryDetile's exact-XOR fast path (PS5 swizzle modes 5/9/24/27) factors the
|
||||
// TryDetile's exact-XOR fast path (PS5 swizzle modes 1/5/9/24/27) factors the
|
||||
// AddrLib bit-interleave into independent per-column X and per-row Y terms so
|
||||
// the inner loop is one array load and one XOR instead of a 16-bit interleave.
|
||||
// These tests pin that the factored output stays byte-identical to the direct
|
||||
@@ -84,6 +84,50 @@ public sealed class GnmTilingDetileTests
|
||||
}
|
||||
}
|
||||
|
||||
// Gen5 Standard256B (mode 1) uses the 8-bit AddrLib S equation, not the
|
||||
// generic StandardSwizzle bit-interleave. Pin that TryDetile recovers a
|
||||
// known linear fill placed with that equation.
|
||||
private static readonly (uint XMask, uint YMask)[] Standard256_1Bpp =
|
||||
[
|
||||
(1u << 0, 0), (1u << 1, 0), (1u << 2, 0), (1u << 3, 0),
|
||||
(0, 1u << 0), (0, 1u << 1), (0, 1u << 2), (0, 1u << 3),
|
||||
];
|
||||
|
||||
[Theory]
|
||||
[InlineData(32, 32)]
|
||||
[InlineData(64, 48)]
|
||||
public void TryDetile_ExactXorMode1_MatchesReferenceAddressEquation(
|
||||
int elementsWide,
|
||||
int elementsHigh)
|
||||
{
|
||||
const uint swizzleMode = 1; // Standard256B
|
||||
const int bytesPerElement = 1;
|
||||
const int blockBytes = 256;
|
||||
const int blockWidth = 16;
|
||||
const int blockHeight = 16;
|
||||
var blocksPerRow = (elementsWide + blockWidth - 1) / blockWidth;
|
||||
var blocksPerColumn = (elementsHigh + blockHeight - 1) / blockHeight;
|
||||
|
||||
var tiled = new byte[blocksPerRow * blocksPerColumn * blockBytes];
|
||||
for (var y = 0; y < elementsHigh; y++)
|
||||
{
|
||||
for (var x = 0; x < elementsWide; x++)
|
||||
{
|
||||
var blockIndex = (long)(y / blockHeight) * blocksPerRow + (x / blockWidth);
|
||||
var sourceByte = (int)(blockIndex * blockBytes +
|
||||
ReferenceOffset((uint)x, (uint)y, Standard256_1Bpp));
|
||||
tiled[sourceByte] = (byte)(y * elementsWide + x);
|
||||
}
|
||||
}
|
||||
|
||||
var linear = new byte[elementsWide * elementsHigh * bytesPerElement];
|
||||
Assert.True(GnmTiling.TryDetile(tiled, linear, swizzleMode, elementsWide, elementsHigh, bytesPerElement));
|
||||
for (var i = 0; i < elementsWide * elementsHigh; i++)
|
||||
{
|
||||
Assert.Equal((byte)i, linear[i]);
|
||||
}
|
||||
}
|
||||
|
||||
// GetDetileParams must reproduce TryDetile bit-for-bit: the CPU fallback and
|
||||
// the GPU compute kernel both consume these params, so a detile driven purely
|
||||
// by DetileParams (the shared addressing formula the kernel runs) must equal
|
||||
@@ -94,8 +138,8 @@ public sealed class GnmTilingDetileTests
|
||||
[InlineData(9u, 4, 300, 300)] // 64 KiB standard (exact-XOR)
|
||||
[InlineData(24u, 4, 128, 256)] // 64 KiB RB+ Z_X (exact-XOR)
|
||||
[InlineData(5u, 4, 200, 120)] // 4 KiB standard (exact-XOR)
|
||||
[InlineData(1u, 4, 64, 64)] // 256 B standard (exact-XOR)
|
||||
[InlineData(8u, 4, 128, 128)] // 64 KiB Z (block-table path)
|
||||
[InlineData(1u, 4, 64, 64)] // 256 B standard (block-table path)
|
||||
public void GetDetileParams_ReproducesTryDetile(uint mode, int bpp, int w, int h)
|
||||
{
|
||||
var p = GnmTiling.GetDetileParams(mode, bpp, w, h);
|
||||
|
||||
Reference in New Issue
Block a user