mirror of
https://github.com/par274/sharpemu.git
synced 2026-07-31 23:19:44 +08:00
fix(gta): restore wiped GTA foundation and gameplay path (PPSA04264) (#650)
* fix(kernel): implement APR ResolveFilepathsWithPrefixToIdsAndFileSizes Resource streamers resolve relative paths against a shared prefix; without this HLE every call returned NOT_FOUND and assets never got real ids/sizes. * fix(remoteplay): stub Initialize and GetConnectionStatus as disconnected Titles probe Remote Play during pad/network bring-up; unresolved imports returned NOT_FOUND. Report initialized + disconnected so callers take the normal offline path. * fix(agc): accept Gen5 hull shaders that omit PGM_LO/HI in CreateShader Type-5 headers can start with RSRC1/RSRC2; rejecting them left null handles and Main Thread AVs. Scan the SH table and skip PGM patch when absent. Co-authored-by: Cursor <cursoragent@cursor.com> * fix(kernel): reject getdents on file fds and emit . / .. for empty dirs Returning rax=0 for non-directory or empty listings looked like EOF and let GTA treat the fd as a pointer (fiWriteAsyncDataWorker AV at 0xB1). * fix(hle): enable GuestImageWriteTracker CPU sync on Windows Windows previously hard-disabled the tracker, so CPU-written guest planes never marked dirty and host textures stayed empty. Arm pages with VirtualProtect, handle write AVs in VEH, and warm/test on VirtualAlloc memory so protect cannot poison the CRT heap. * fix(agc): skip CB metadata draws for EliminateFastClear/Fmask/DCC CB_COLOR_CONTROL modes 2/5/6 are colour-buffer metadata ops; applying the bound shader as a normal colour draw corrupts subsequent composites. Decode MODE from bits [6:4] and return before translate. * fix(agc): merge Prospero attrib-table formats onto IR vertex inputs IR-discovered BufferLoadFormat often keeps a stale float sharp format; patch DataFormat/offset from the AGC attrib table (semantic index), allow offen fetches, and map quirks 113/121 through NarrowVk for host vertex input. * fix(audio): harden AudioOut2 stack out-buffer writes against canary smash Titles that stack-allocate AudioOut2 outs next to the frame canary were corrupted by oversized or mistyped HLE writes; keep ContextPush pacing. * Revert "fix(memory): reserve only large regions (#608)" This reverts commit8f9456229a. * fix(gpu): decode Gen5 R16 and RG32 render-target formats * fix(audio): AudioOut2 host beds, deeper waveOut queue, AJM MP3 GTA V Enhanced routes intro/menu audio through AudioOut2 and FMOD's AJM MP3 path. Wire PortCreate/PortSetAttributes/ContextPush to dual host stereo streams, deepen WinMM queue to 128KiB, and decode AJM codec 0 with a stateful NLayer helper so menu music is not silent. * fix(agc): map PS interpolants via SPI_PS_INPUT_CNTL semantics Identity ATTR→param wiring ignored hardware remapping, so UI draws got wrong (or empty) interpolants. Pack CNTL from matched PS/GS semantics, thread it into Vulkan/Metal as Location/Flat, and fingerprint it in the graphics shader cache key. * fix(agc): rect-list/NGG strips, Index8 expand, and GE_INDX_OFFSET NGG single-rect UI needs triangle-strip expansion; Prospero Index8 must expand to host u16; glyphs need base vertex from GE_INDX_OFFSET. Skip param-less rect-lists instead of inventing colour draws. * fix(np): report GTA Story Mode addcont entitlements as owned NpEntitlementAccess was returning an empty add-on list, so GTA V Enhanced offered Buy Story Mode. Publish the installed license labels and stub premium-event registration so offline sessions take the owned path. * fix(cpu): prefer native workers for all guest entry stubs Route thread entry, continuation, and main entry through RunGuestEntryStub so guest stubs are not invoked above CLR-managed frames (UnmanagedCallersOnly FailFast). Keep requireNativeWorker for tbb_thead; other paths prefer workers with calli fallback. * fix(agc): implement Rewind/Jump writers and IT_REWIND waits GTA Subrender AVs came from AcbJumpGetSize / DcbRewind returning NOT_FOUND as packet sizes. Add IT_REWIND and INDIRECT_BUFFER writers, patch SetRewindState into the GPU wait registry, and nest-parse 4-dword jumps. * fix(gpu): use AddrLib ExactXor for Gen5 Standard256B (mode 1) Mode 5 already had Standard4K ExactXor; mode 1 still used the generic StandardSwizzle block table, which mis-detiles Gen5 UI atlases. * Revert "fix(cpu): prefer native workers for all guest entry stubs" This reverts commit31c4db0d38. * fix(memory): commit-first large maps; reserve only on failure Replace the #608 always-reserve-only exact-map path with allocate-first and lazy reserve fallback when a huge non-exec commit cannot be satisfied. Prime and widen GetPointer commit so the fallback path is safer for native walkers. Drops the need for a hard #608 revert. * [Agc] Implement fused shader half exports * fix(agc): accept optional hull state in CreatePrimState Port the CreatePrimState hull-optional path from #583 so fused HS pipelines (GTA) are not rejected with INVALID_ARGUMENT. Geometry-derived CX/UC writes are unchanged; hull is traced only. * fix(videoout): restore thread-safe VulkanHostBufferPool (#564) The6db095ewipe dropped CasualcoderDev's lock-ordering-safe pool. Concurrent Return/TryTake without the gate races after the first present and can hang the submit path. * Revert "fix(agc): implement Rewind/Jump writers and IT_REWIND waits" This reverts commitbec77bf083. * test(memory): align lazy-commit expectations with commit-first policy Fake hosts must reject Allocate so reserve-only paths still run, and GetPointer asserts the 32 MiB prime range including AlignUp spill. * diag(gpu): log guest-queue backlog breakdown under backpressure Rate-limit top work types and ordered debugName prefixes when the Vulkan guest work queue stalls, so North Yankton logs show acquire/label vs draw traffic instead of only VulkanOrderedGuestAction. * perf(agc): coalesce acquire flushes and batch non-DMA label wakes Flush pending ACQUIRE_MEM invalidation at draw/dispatch/dma/flip boundaries instead of before every packet, and complete release/write-data producers in the same ordered action so load paths enqueue far fewer VulkanOrderedGuestAction items. * perf(gpu): wait for ordered-action fences and keep draining sync On Windows/Linux, block briefly for queue-visibility fences instead of deferring the whole logical queue for the tick. Prefer ordered sync/flip heads under backlog pressure, and keep macOS non-blocking defer behavior. * perf(gpu): raise sync-item ceiling above payload guest-work cap Apply SHARPEMU_PENDING_GUEST_WORK_ITEMS mainly to compute/draw/image payload work, and allow a higher SHARPEMU_PENDING_GUEST_SYNC_ITEMS ceiling for zero-payload ordered actions and flip markers. Keep the byte budget as the RAM safety valve. * fix(gta): stub Voice ports and implement sceKernelCheckReachability Resolve North Yankton-path Voice Create/Delete/Connect/Disconnect/End NIDs and EnumerationThread reachability checks so leftover unresolved imports are not on the critical path. * diag(gta): arm flip/present/wait probes after North Audio Rate-limited load_progress TRACE for flip submit, ordered flip enqueue, present taken/not-taken, and GPU wait backlog so North Yankton freezes can be classified without full AGC tracing. * fix(ampr): restore sequential offset=-1 reads for streamer packs Re-wire PakDirectoryTracker into sceAmprAprCommandBufferReadFile (dropped in #216) so RAGE sequential pack reads no longer fail while the North Yankton UI keeps flipping. Also rate-limit CheckReachability miss paths for EnumerationThread diagnosis. * fix(hle/videoout): Windows GuestImage opt-in and keep GTA intro without sync Default the tracker off on Windows to avoid VirtualProtect thrash, gate AGC texel-copy skips on Enabled so guest Bink planes keep shipping pixels, and drain CPU-written images on the present thread when sync is opted in. * fix(videoout): probe guest content when tracker off so UI can skip copies Restores upload-known/texture-cache skips for Dead Cells menus, and uses a sparse guest-memory fingerprint when GuestImageWriteTracker is disabled so CPU-updated Bink planes still force texel copies for GTA intro. * fix(audio): keep 128KiB host queue AudioOut2-only Restore the default 32 KiB (~171 ms) PCM bed for classic AudioOut so titles like Dreaming Sarah stay in sync; only AudioOut2 opens the deeper queue needed for bursty FMOD Push on GTA. --------- Co-authored-by: samto6 <123419830+samto6@users.noreply.github.com>
This commit is contained in:
MarcelMediaDev
+1392
-207
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,49 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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namespace SharpEmu.Libs.Agc;
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/// <summary>Prospero/AGC IndexType helpers (gpu_defs / renderDraw index8 expand).</summary>
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internal static class AgcIndexHelpers
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{
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internal enum ProsperoIndexType : uint
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{
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Index16 = 0,
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Index32 = 1,
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Index8 = 2,
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}
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internal static ProsperoIndexType Decode(uint raw) =>
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(raw & 0x3u) switch
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{
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1 => ProsperoIndexType.Index32,
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2 => ProsperoIndexType.Index8,
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_ => ProsperoIndexType.Index16,
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};
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internal static int GetGuestStrideBytes(ProsperoIndexType indexType) =>
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indexType switch
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{
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ProsperoIndexType.Index32 => sizeof(uint),
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ProsperoIndexType.Index8 => sizeof(byte),
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_ => sizeof(ushort),
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};
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/// <summary>Expand guest u8 indices to host u16 (Vulkan/Metal bindable).</summary>
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internal static void ExpandIndex8ToU16(ReadOnlySpan<byte> source, Span<byte> destination)
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{
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if (destination.Length < source.Length * sizeof(ushort))
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{
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throw new ArgumentException("destination too small for u8->u16 expansion.");
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}
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for (var index = 0; index < source.Length; index++)
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{
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BinaryPrimitives.WriteUInt16LittleEndian(
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destination.Slice(index * sizeof(ushort), sizeof(ushort)),
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source[index]);
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}
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}
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}
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@@ -0,0 +1,107 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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namespace SharpEmu.Libs.Agc;
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/// <summary>
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/// Shared Prospero/AGC primitive-type helpers (renderDraw / gpu_defs).
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/// </summary>
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internal static class AgcPrimitiveHelpers
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{
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internal const uint PrimitiveRectList = 7;
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internal const uint PrimitiveRectListLegacy = 0x11;
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internal enum GsOutputPrimitiveType : uint
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{
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Points = 0,
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Lines = 1,
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Triangles = 2,
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Rectangle2D = 3,
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RectList = 4,
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}
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internal static bool IsRectListPrimitive(uint primitiveType) =>
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primitiveType is PrimitiveRectList or PrimitiveRectListLegacy;
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/// <summary>
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/// Maps draw prim type to VGT_GS_OUT_PRIM_TYPE when NGG is not enabled
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/// on the GS (GraphicsPrimitiveTypeToGsOut).
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/// </summary>
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internal static uint PrimitiveTypeToGsOut(uint primitiveType) =>
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primitiveType switch
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{
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1 => (uint)GsOutputPrimitiveType.Points, // PointList
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2 or 3 or 10 or 11 or 18 => (uint)GsOutputPrimitiveType.Lines,
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PrimitiveRectList => (uint)GsOutputPrimitiveType.Rectangle2D,
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PrimitiveRectListLegacy => (uint)GsOutputPrimitiveType.RectList,
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_ => (uint)GsOutputPrimitiveType.Triangles,
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};
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/// <summary>
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/// Rect-list auto-draw topology selection.
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/// NGG single-rect UI quads (DualSense prompts) submit count 1/3/4 and
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/// must become a 4-vert triangle strip — even when the VS has embedded
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/// vertex-buffer fetches (those still show up as host VBs). Indexed and
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/// larger auto counts stay triangle list so the loading video is safe.
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/// </summary>
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internal static bool ShouldDrawRectListAsTriangleStrip(
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uint primitiveType,
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bool indexed,
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uint vertexCount,
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bool hasVertexBuffers = false)
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{
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_ = hasVertexBuffers;
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if (indexed || !IsRectListPrimitive(primitiveType))
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{
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return false;
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}
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if (primitiveType == PrimitiveRectListLegacy)
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{
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return true;
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}
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// NGG kRectList: strip for auto + ngg_rectlist_draw.
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// Restrict to the single-rect counts GTA UI actually submits.
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return vertexCount is 1 or 3 or 4;
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}
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/// <summary>
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/// Host vertex count for auto rect-list draws that expand to a strip.
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/// NGG single-rect: always 4. Legacy 0x11: 3 -> 4.
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/// </summary>
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internal static uint GetRectListDrawVertexCount(
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uint primitiveType,
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uint vertexCount,
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bool indexed,
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bool hasVertexBuffers = false)
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{
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if (!ShouldDrawRectListAsTriangleStrip(
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primitiveType,
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indexed,
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vertexCount,
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hasVertexBuffers))
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{
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return vertexCount;
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}
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if (primitiveType == PrimitiveRectList)
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{
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return 4;
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}
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if (primitiveType == PrimitiveRectListLegacy && vertexCount == 3)
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{
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return 4;
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}
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return vertexCount;
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}
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/// <summary>
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/// Legacy helper — prefer
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/// <see cref="ShouldDrawRectListAsTriangleStrip"/>.
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/// </summary>
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internal static bool IsRectListTriangleStrip(uint primitiveType) =>
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IsRectListPrimitive(primitiveType);
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}
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@@ -0,0 +1,788 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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namespace SharpEmu.Libs.Agc;
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/// <summary>
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/// AGC embedded vertex metadata. Locates
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/// PtrVertexBufferTable / PtrVertexAttribDescTable and builds authoritative
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/// attribute layouts that draw translation merges onto IR-discovered fetches.
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/// </summary>
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internal static class AgcVertexMetadata
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{
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private const ushort IllegalDirectOffset = 0xFFFF;
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private const ulong ShaderUserDataOffset = 0x08;
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private const ulong ShaderInputSemanticsOffset = 0x30;
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private const ulong ShaderNumInputSemanticsOffset = 0x50;
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internal enum AgcDirectResourceType : uint
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{
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PtrVertexBufferTable = 8,
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PtrVertexAttribDescTable = 10,
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Last = PtrVertexAttribDescTable,
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}
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internal readonly record struct VertexTableRegisters(
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int VertexBufferReg,
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int VertexAttribReg,
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uint InputSemanticsCount,
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ulong InputSemanticsAddress);
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/// <summary>
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/// One AGC attrib-table resource.
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/// Representation: <see cref="SharpBase"/> is the V# base; attribute byte
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/// offset is applied as <see cref="OffsetBytes"/> (Vulkan bind offset),
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/// not folded into the base — avoids double-counting when the IR prolog
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/// already bumped the sharp address.
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/// </summary>
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internal readonly record struct MetadataVertexResource(
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uint Location,
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uint Semantic,
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uint HardwareMapping,
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uint SizeInElements,
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ulong SharpBase,
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uint Stride,
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uint OffsetBytes,
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uint DataFormat,
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uint NumberFormat,
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uint ComponentCount,
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bool PerInstance);
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/// <summary>
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/// Reads AGC user-data direct-resource offsets for the ES header mapped to
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/// <paramref name="shaderCodeAddress"/>. Returns false when the header is
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/// unknown or the tables are absent (attribute-less clears).
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/// </summary>
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internal static bool TryGetVertexTableRegisters(
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CpuContext ctx,
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ulong shaderCodeAddress,
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ulong shaderHeaderAddress,
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out VertexTableRegisters registers)
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{
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registers = new VertexTableRegisters(-1, -1, 0, 0);
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if (shaderHeaderAddress == 0 ||
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!TryReadUInt64(ctx, shaderHeaderAddress + ShaderUserDataOffset, out var userDataAddress) ||
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userDataAddress == 0)
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{
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return false;
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}
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// ShaderUserData layout:
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// 0x00: uint16_t* direct_resource_offset
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// 0x08: sharp_resource_offset[4]
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// 0x28: eud_size_dw, srt_size_dw
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// 0x2C: direct_resource_count
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if (!TryReadUInt64(ctx, userDataAddress, out var directResourceOffset) ||
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!TryReadUInt16(ctx, userDataAddress + 0x2C, out var directResourceCount))
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{
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return false;
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}
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var maxTypes = (uint)AgcDirectResourceType.Last + 1u;
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if (directResourceCount > maxTypes || directResourceOffset == 0)
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{
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return false;
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}
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var vertexBufferReg = -1;
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var vertexAttribReg = -1;
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for (uint type = 0; type < directResourceCount; type++)
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{
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if (!TryReadUInt16(
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ctx,
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directResourceOffset + (type * sizeof(ushort)),
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out var reg) ||
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reg == IllegalDirectOffset)
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{
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continue;
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}
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switch ((AgcDirectResourceType)type)
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{
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case AgcDirectResourceType.PtrVertexBufferTable:
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vertexBufferReg = reg;
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break;
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case AgcDirectResourceType.PtrVertexAttribDescTable:
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vertexAttribReg = reg;
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break;
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}
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}
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if (vertexBufferReg < 0 || vertexAttribReg < 0)
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{
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return false;
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}
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if (!TryReadUInt64(
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ctx,
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shaderHeaderAddress + ShaderInputSemanticsOffset,
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out var inputSemanticsAddress) ||
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!TryReadUInt32(
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ctx,
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shaderHeaderAddress + ShaderNumInputSemanticsOffset,
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out var inputSemanticsCount) ||
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inputSemanticsCount == 0 ||
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inputSemanticsAddress == 0)
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{
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return false;
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}
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registers = new VertexTableRegisters(
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vertexBufferReg,
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vertexAttribReg,
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inputSemanticsCount,
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inputSemanticsAddress);
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return true;
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}
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/// <summary>
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/// Builds attrib resources from AGC input_semantics + tables.
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/// ShaderSemantic packing:
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/// bits [7:0] semantic → attrib table index
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/// bits [15:8] hardware_mapping → VGPR destination
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/// bits [19:16] size_in_elements
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/// </summary>
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internal static bool TryBuildVertexResourcesFromMetadata(
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CpuContext ctx,
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IReadOnlyList<uint> scalarRegisters,
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VertexTableRegisters tables,
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out IReadOnlyList<MetadataVertexResource> resources)
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{
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resources = Array.Empty<MetadataVertexResource>();
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if (tables.VertexAttribReg < 0 ||
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tables.VertexBufferReg < 0 ||
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tables.VertexAttribReg + 1 >= scalarRegisters.Count ||
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||||
tables.VertexBufferReg + 1 >= scalarRegisters.Count ||
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tables.InputSemanticsCount == 0)
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{
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||||
return false;
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}
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||||
var attribTable =
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((ulong)scalarRegisters[tables.VertexAttribReg + 1] << 32) |
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scalarRegisters[tables.VertexAttribReg];
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||||
var bufferTable =
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((ulong)scalarRegisters[tables.VertexBufferReg + 1] << 32) |
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scalarRegisters[tables.VertexBufferReg];
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||||
if (attribTable == 0 || bufferTable == 0)
|
||||
{
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||||
return false;
|
||||
}
|
||||
|
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var built = new List<MetadataVertexResource>((int)tables.InputSemanticsCount);
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||||
for (uint i = 0; i < tables.InputSemanticsCount; i++)
|
||||
{
|
||||
if (!TryReadUInt32(
|
||||
ctx,
|
||||
tables.InputSemanticsAddress + (i * sizeof(uint)),
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||||
out var semanticWord))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
// Attrib index is semantic bits [7:0], not hardware_mapping.
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||||
var semantic = semanticWord & 0xFFu;
|
||||
var hardwareMapping = (semanticWord >> 8) & 0xFFu;
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var sizeInElements = (semanticWord >> 16) & 0xFu;
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if (!TryReadUInt32(ctx, attribTable + (semantic * sizeof(uint)), out var attribWord))
|
||||
{
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||||
return false;
|
||||
}
|
||||
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||||
// Attrib dword: buffer index [4:0], format [13:5], offset [25:14], fetch [26].
|
||||
var bufferIndex = attribWord & 0x1Fu;
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||||
var format = (attribWord >> 5) & 0x1FFu;
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var offset = (attribWord >> 14) & 0xFFFu;
|
||||
var fetchIndex = (attribWord >> 26) & 0x1u;
|
||||
var sharpAddress = bufferTable + (bufferIndex * 16u);
|
||||
if (!TryReadUInt32(ctx, sharpAddress, out var sharp0) ||
|
||||
!TryReadUInt32(ctx, sharpAddress + 4, out var sharp1))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
var sharpBase = sharp0 | ((ulong)(sharp1 & 0xFFFFu) << 32);
|
||||
var stride = (sharp1 >> 16) & 0x3FFFu;
|
||||
if (sharpBase == 0 || stride == 0)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
var fallbackComponents = sizeInElements != 0 ? sizeInElements : 4u;
|
||||
var (dataFormat, numberFormat, components) =
|
||||
MapAttribFormat(format, fallbackComponents);
|
||||
built.Add(new MetadataVertexResource(
|
||||
Location: i,
|
||||
Semantic: semantic,
|
||||
HardwareMapping: hardwareMapping,
|
||||
SizeInElements: sizeInElements,
|
||||
SharpBase: sharpBase,
|
||||
Stride: stride,
|
||||
OffsetBytes: offset,
|
||||
DataFormat: dataFormat,
|
||||
NumberFormat: numberFormat,
|
||||
ComponentCount: components,
|
||||
PerInstance: fetchIndex != 0));
|
||||
}
|
||||
|
||||
if (built.Count == 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
resources = built;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Patch IR-discovered fetches from the attrib table onto the V# format/offset.
|
||||
/// Prefer 1:1 Location pairing when counts match on one interleaved stream
|
||||
/// (GTA UI glyphs). Otherwise match by stride + byte offset. Never rebases
|
||||
/// BaseAddress/Data/Location/Pc/PerInstance.
|
||||
/// </summary>
|
||||
internal static IReadOnlyList<Gen5VertexInputBinding> MergeVertexInputsFromMetadata(
|
||||
CpuContext ctx,
|
||||
IReadOnlyList<uint> scalarRegisters,
|
||||
VertexTableRegisters tables,
|
||||
IReadOnlyList<Gen5VertexInputBinding> discovered)
|
||||
{
|
||||
if (discovered.Count == 0 ||
|
||||
!TryBuildVertexResourcesFromMetadata(
|
||||
ctx,
|
||||
scalarRegisters,
|
||||
tables,
|
||||
out var resources))
|
||||
{
|
||||
return discovered;
|
||||
}
|
||||
|
||||
if (TryMergeByLocationPairing(discovered, resources, out var paired))
|
||||
{
|
||||
return paired;
|
||||
}
|
||||
|
||||
var merged = new List<Gen5VertexInputBinding>(discovered.Count);
|
||||
var usedResources = new bool[resources.Count];
|
||||
var changed = false;
|
||||
foreach (var input in discovered)
|
||||
{
|
||||
if (!TryMatchMetadataResource(input, resources, usedResources, out var resource, out var fillOffset))
|
||||
{
|
||||
merged.Add(input);
|
||||
continue;
|
||||
}
|
||||
|
||||
var refined = ApplyMetadataFormat(input, resource, fillOffset);
|
||||
changed |= refined != input;
|
||||
merged.Add(refined);
|
||||
}
|
||||
|
||||
return changed ? merged : discovered;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// When discovery and metadata describe the same interleaved stream with
|
||||
/// equal attribute counts, pair by sorted Location (semantic order).
|
||||
/// Keeps each binding's Pc/Location for SPIR-V; overlays format + offset.
|
||||
/// </summary>
|
||||
private static bool TryMergeByLocationPairing(
|
||||
IReadOnlyList<Gen5VertexInputBinding> discovered,
|
||||
IReadOnlyList<MetadataVertexResource> resources,
|
||||
out IReadOnlyList<Gen5VertexInputBinding> merged)
|
||||
{
|
||||
merged = discovered;
|
||||
if (discovered.Count != resources.Count || discovered.Count == 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
var orderedInputs = discovered.OrderBy(static input => input.Location).ToArray();
|
||||
var orderedResources = resources.OrderBy(static resource => resource.Location).ToArray();
|
||||
var streamBase = orderedResources[0].SharpBase;
|
||||
var streamStride = orderedResources[0].Stride;
|
||||
for (var index = 0; index < orderedResources.Length; index++)
|
||||
{
|
||||
var resource = orderedResources[index];
|
||||
var input = orderedInputs[index];
|
||||
if (resource.SharpBase != streamBase ||
|
||||
resource.Stride != streamStride ||
|
||||
(input.Stride != 0 && input.Stride != streamStride) ||
|
||||
!IsSameVertexStream(input, resource))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
var byPc = new Dictionary<uint, Gen5VertexInputBinding>(discovered.Count);
|
||||
var changed = false;
|
||||
for (var index = 0; index < orderedInputs.Length; index++)
|
||||
{
|
||||
var input = orderedInputs[index];
|
||||
var resource = orderedResources[index];
|
||||
var fillOffset = input.BaseAddress == resource.SharpBase ||
|
||||
IsAddressInsideCapturedSpan(input, resource.SharpBase);
|
||||
var refined = ApplyMetadataFormat(input, resource, fillOffset);
|
||||
changed |= refined != input;
|
||||
byPc[input.Pc] = refined;
|
||||
}
|
||||
|
||||
if (!changed)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
var result = new Gen5VertexInputBinding[discovered.Count];
|
||||
for (var index = 0; index < discovered.Count; index++)
|
||||
{
|
||||
result[index] = byPc[discovered[index].Pc];
|
||||
}
|
||||
|
||||
merged = result;
|
||||
return true;
|
||||
}
|
||||
|
||||
private static Gen5VertexInputBinding ApplyMetadataFormat(
|
||||
Gen5VertexInputBinding input,
|
||||
MetadataVertexResource resource,
|
||||
bool fillOffsetBytes)
|
||||
{
|
||||
var components = input.ComponentCount != 0 &&
|
||||
input.ComponentCount < resource.ComponentCount
|
||||
? input.ComponentCount
|
||||
: resource.ComponentCount;
|
||||
|
||||
return input with
|
||||
{
|
||||
DataFormat = resource.DataFormat,
|
||||
NumberFormat = resource.NumberFormat,
|
||||
ComponentCount = components,
|
||||
OffsetBytes = fillOffsetBytes ? resource.OffsetBytes : input.OffsetBytes,
|
||||
};
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Legacy entry point — forwards to <see cref="MergeVertexInputsFromMetadata"/>.
|
||||
/// </summary>
|
||||
internal static IReadOnlyList<Gen5VertexInputBinding> RefineVertexInputs(
|
||||
CpuContext ctx,
|
||||
IReadOnlyList<uint> scalarRegisters,
|
||||
VertexTableRegisters tables,
|
||||
IReadOnlyList<Gen5VertexInputBinding> discovered) =>
|
||||
MergeVertexInputsFromMetadata(ctx, scalarRegisters, tables, discovered);
|
||||
|
||||
/// <summary>
|
||||
/// Collects SBufferLoad / SLoad PCs that read the AGC attrib or buffer
|
||||
/// tables (embedded-fetch prolog). Those loads are executed on the
|
||||
/// CPU during scalar evaluation; once vertex inputs are bound they must
|
||||
/// not run again as live SSBOs on the GPU.
|
||||
/// </summary>
|
||||
internal static HashSet<uint> CollectFetchPrologPcs(
|
||||
Gen5ShaderProgram program,
|
||||
VertexTableRegisters tables)
|
||||
{
|
||||
var pcs = new HashSet<uint>();
|
||||
if (tables.VertexAttribReg < 0 || tables.VertexBufferReg < 0)
|
||||
{
|
||||
return pcs;
|
||||
}
|
||||
|
||||
var tableRegs = new HashSet<uint>
|
||||
{
|
||||
(uint)tables.VertexAttribReg,
|
||||
(uint)tables.VertexAttribReg + 1u,
|
||||
(uint)tables.VertexBufferReg,
|
||||
(uint)tables.VertexBufferReg + 1u,
|
||||
};
|
||||
|
||||
foreach (var instruction in program.Instructions)
|
||||
{
|
||||
var isScalarLoad =
|
||||
instruction.Opcode.StartsWith("SBufferLoad", StringComparison.Ordinal) ||
|
||||
instruction.Opcode.StartsWith("SLoad", StringComparison.Ordinal);
|
||||
if (!isScalarLoad)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
// SMEM loads encode the scalar base pointer in Sources[0].
|
||||
if (instruction.Sources.Count > 0 &&
|
||||
instruction.Sources[0] is
|
||||
{
|
||||
Kind: Gen5OperandKind.ScalarRegister,
|
||||
Value: var scalarBase,
|
||||
} &&
|
||||
tableRegs.Contains(scalarBase))
|
||||
{
|
||||
pcs.Add(instruction.Pc);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (instruction.Control is Gen5BufferMemoryControl buffer &&
|
||||
tableRegs.Contains(buffer.ScalarResource))
|
||||
{
|
||||
pcs.Add(instruction.Pc);
|
||||
}
|
||||
}
|
||||
|
||||
return pcs;
|
||||
}
|
||||
|
||||
private static bool TryMatchMetadataResource(
|
||||
Gen5VertexInputBinding input,
|
||||
IReadOnlyList<MetadataVertexResource> resources,
|
||||
bool[] usedResources,
|
||||
out MetadataVertexResource resource,
|
||||
out bool fillOffsetBytes)
|
||||
{
|
||||
resource = default;
|
||||
fillOffsetBytes = false;
|
||||
var bestScore = int.MinValue;
|
||||
var bestIndex = -1;
|
||||
var bestFillOffset = false;
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (usedResources[index])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
var candidate = resources[index];
|
||||
if (candidate.Stride != 0 &&
|
||||
input.Stride != 0 &&
|
||||
candidate.Stride != input.Stride)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!IsSameVertexStream(input, candidate))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
var attrAddress = candidate.SharpBase + candidate.OffsetBytes;
|
||||
var score = int.MinValue;
|
||||
var fillOffset = false;
|
||||
|
||||
// Post-capture interleaved: shared BaseAddress, distinct OffsetBytes.
|
||||
if (input.OffsetBytes == candidate.OffsetBytes &&
|
||||
(input.BaseAddress == candidate.SharpBase ||
|
||||
IsAddressInsideCapturedSpan(input, candidate.SharpBase)))
|
||||
{
|
||||
score = 400;
|
||||
}
|
||||
// IR prolog baked attrib offset into the V# base.
|
||||
else if (input.BaseAddress == attrAddress)
|
||||
{
|
||||
score = 350;
|
||||
}
|
||||
// Discovery never saw the attrib offset — only safe when this
|
||||
// resource's offset uniquely identifies it among unused entries.
|
||||
else if (input.BaseAddress == candidate.SharpBase &&
|
||||
input.OffsetBytes == 0 &&
|
||||
candidate.OffsetBytes != 0 &&
|
||||
IsUniqueUnusedOffset(resources, usedResources, candidate.OffsetBytes, index))
|
||||
{
|
||||
score = 300;
|
||||
fillOffset = true;
|
||||
}
|
||||
else if (input.BaseAddress == candidate.SharpBase &&
|
||||
input.OffsetBytes == 0 &&
|
||||
candidate.OffsetBytes == 0)
|
||||
{
|
||||
score = 250;
|
||||
}
|
||||
|
||||
if (score > bestScore)
|
||||
{
|
||||
bestScore = score;
|
||||
bestIndex = index;
|
||||
bestFillOffset = fillOffset;
|
||||
}
|
||||
}
|
||||
|
||||
// Require an offset-aware match. Bare SharpBase ties (score 250) are
|
||||
// only accepted when a single unused resource remains for that stream.
|
||||
if (bestIndex < 0 || bestScore < 300)
|
||||
{
|
||||
if (bestIndex < 0 || bestScore < 250)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
var unusedSameStream = 0;
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (!usedResources[index] && IsSameVertexStream(input, resources[index]))
|
||||
{
|
||||
unusedSameStream++;
|
||||
}
|
||||
}
|
||||
|
||||
if (unusedSameStream != 1)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
usedResources[bestIndex] = true;
|
||||
resource = resources[bestIndex];
|
||||
fillOffsetBytes = bestFillOffset;
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool IsSameVertexStream(
|
||||
Gen5VertexInputBinding input,
|
||||
MetadataVertexResource resource)
|
||||
{
|
||||
if (input.BaseAddress == resource.SharpBase ||
|
||||
input.BaseAddress == resource.SharpBase + resource.OffsetBytes)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
return IsAddressInsideCapturedSpan(input, resource.SharpBase);
|
||||
}
|
||||
|
||||
private static bool IsAddressInsideCapturedSpan(
|
||||
Gen5VertexInputBinding input,
|
||||
ulong address) =>
|
||||
input.DataLength > 0 &&
|
||||
address >= input.BaseAddress &&
|
||||
address < input.BaseAddress + (ulong)input.DataLength;
|
||||
|
||||
private static bool IsUniqueUnusedOffset(
|
||||
IReadOnlyList<MetadataVertexResource> resources,
|
||||
bool[] usedResources,
|
||||
uint offsetBytes,
|
||||
int candidateIndex)
|
||||
{
|
||||
for (var index = 0; index < resources.Count; index++)
|
||||
{
|
||||
if (index == candidateIndex || usedResources[index])
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
if (resources[index].OffsetBytes == offsetBytes)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Attrib-table format
|
||||
/// fields are VertexAttribFormat; V# / Vulkan paths need BufferFormat.
|
||||
/// Unknown values pass through (already BufferFormat).
|
||||
/// </summary>
|
||||
private static uint VertexAttribFormatToBufferFormat(uint format) =>
|
||||
format switch
|
||||
{
|
||||
0 => 0, // Invalid
|
||||
4 => 1, // k8UNorm
|
||||
8 => 2, // k8SNorm
|
||||
12 => 3, // k8UScaled
|
||||
16 => 4, // k8SScaled
|
||||
20 => 5, // k8UInt
|
||||
24 => 6, // k8SInt
|
||||
28 => 7, // k16UNorm
|
||||
32 => 8, // k16SNorm
|
||||
36 => 9, // k16UScaled
|
||||
40 => 10, // k16SScaled
|
||||
44 => 11, // k16UInt
|
||||
48 => 12, // k16SInt
|
||||
52 => 13, // k16Float
|
||||
57 => 14, // k8_8UNorm
|
||||
61 => 15, // k8_8SNorm
|
||||
65 => 16, // k8_8UScaled
|
||||
69 => 17, // k8_8SScaled
|
||||
73 => 18, // k8_8UInt
|
||||
77 => 19, // k8_8SInt
|
||||
80 => 20, // k32UInt
|
||||
84 => 21, // k32SInt
|
||||
88 => 22, // k32Float
|
||||
93 => 23, // k16_16UNorm
|
||||
97 => 24, // k16_16SNorm
|
||||
101 => 25, // k16_16UScaled
|
||||
105 => 26, // k16_16SScaled
|
||||
109 => 27, // k16_16UInt
|
||||
113 => 28, // k16_16SInt
|
||||
117 => 29, // k16_16Float
|
||||
122 => 30, // k11_11_10UNorm
|
||||
126 => 31,
|
||||
130 => 32,
|
||||
134 => 33,
|
||||
138 => 34,
|
||||
142 => 35,
|
||||
146 => 36,
|
||||
150 => 37, // k10_11_11UNorm
|
||||
154 => 38,
|
||||
158 => 39,
|
||||
162 => 40,
|
||||
166 => 41,
|
||||
170 => 42,
|
||||
174 => 43,
|
||||
179 => 44, // k2_10_10_10UNorm
|
||||
183 => 45,
|
||||
187 => 46,
|
||||
191 => 47,
|
||||
195 => 48,
|
||||
199 => 49,
|
||||
203 => 50, // k10_10_10_2UNorm
|
||||
207 => 51,
|
||||
211 => 52,
|
||||
215 => 53,
|
||||
219 => 54,
|
||||
223 => 55,
|
||||
227 => 56, // k8_8_8_8UNorm
|
||||
231 => 57,
|
||||
235 => 58,
|
||||
239 => 59,
|
||||
243 => 60,
|
||||
247 => 61,
|
||||
249 => 62, // k32_32UInt
|
||||
253 => 63,
|
||||
257 => 64, // k32_32Float
|
||||
263 => 65, // k16_16_16_16UNorm
|
||||
267 => 66,
|
||||
271 => 67,
|
||||
275 => 68,
|
||||
279 => 69,
|
||||
283 => 70,
|
||||
287 => 71, // k16_16_16_16Float
|
||||
290 => 72, // k32_32_32UInt
|
||||
294 => 73,
|
||||
298 => 74,
|
||||
303 => 75, // k32_32_32_32UInt
|
||||
307 => 76,
|
||||
311 => 77, // k32_32_32_32Float
|
||||
_ => format,
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Maps Prospero attrib-table formats onto GNM (DataFormat, NumberFormat,
|
||||
/// Components) for <c>ToVkVertexFormat</c>. Accepts VertexAttribFormat
|
||||
/// or BufferFormat (pass-through). NumberFormat: 0 Unorm, 1 SNorm,
|
||||
/// 2 UScaled, 3 SScaled, 4 UInt, 5 SInt, 7 Float.
|
||||
/// </summary>
|
||||
private static (uint DataFormat, uint NumberFormat, uint Components) MapAttribFormat(
|
||||
uint attribFormat,
|
||||
uint fallbackComponents)
|
||||
{
|
||||
// Prospero VertexAttribFormat quirks before BufferFormat conversion.
|
||||
if (attribFormat == 113)
|
||||
{
|
||||
return (14, 7, 4); // R32G32B32A32_SFLOAT
|
||||
}
|
||||
|
||||
if (attribFormat == 121)
|
||||
{
|
||||
return (5, 7, 2); // R16G16_SFLOAT
|
||||
}
|
||||
|
||||
var bufferFormat = VertexAttribFormatToBufferFormat(attribFormat);
|
||||
|
||||
// Prospero::BufferFormat numeric values (gpu_defs.h).
|
||||
return bufferFormat switch
|
||||
{
|
||||
1 => (1, 0, 1), // k8UNorm
|
||||
2 => (1, 1, 1), // k8SNorm
|
||||
3 => (1, 2, 1), // k8UScaled
|
||||
4 => (1, 3, 1), // k8SScaled
|
||||
5 => (1, 4, 1), // k8UInt
|
||||
6 => (1, 5, 1), // k8SInt
|
||||
7 => (2, 0, 1), // k16UNorm
|
||||
8 => (2, 1, 1), // k16SNorm
|
||||
9 => (2, 2, 1), // k16UScaled
|
||||
10 => (2, 3, 1), // k16SScaled
|
||||
11 => (2, 4, 1), // k16UInt
|
||||
12 => (2, 5, 1), // k16SInt
|
||||
13 => (2, 7, 1), // k16Float
|
||||
14 => (3, 0, 2), // k8_8UNorm
|
||||
15 => (3, 1, 2), // k8_8SNorm
|
||||
16 => (3, 2, 2), // k8_8UScaled
|
||||
17 => (3, 3, 2), // k8_8SScaled
|
||||
18 => (3, 4, 2), // k8_8UInt
|
||||
19 => (3, 5, 2), // k8_8SInt
|
||||
20 => (4, 4, 1), // k32UInt
|
||||
21 => (4, 5, 1), // k32SInt
|
||||
22 => (4, 7, 1), // k32Float
|
||||
23 => (5, 0, 2), // k16_16UNorm
|
||||
24 => (5, 1, 2), // k16_16SNorm
|
||||
25 => (5, 2, 2), // k16_16UScaled
|
||||
26 => (5, 3, 2), // k16_16SScaled
|
||||
27 => (5, 4, 2), // k16_16UInt
|
||||
28 => (5, 5, 2), // k16_16SInt
|
||||
29 => (5, 7, 2), // k16_16Float
|
||||
50 => (9, 0, 4), // k10_10_10_2UNorm
|
||||
51 => (9, 1, 4), // k10_10_10_2SNorm
|
||||
56 => (10, 0, 4), // k8_8_8_8UNorm
|
||||
57 => (10, 1, 4), // k8_8_8_8SNorm
|
||||
58 => (10, 2, 4), // k8_8_8_8UScaled
|
||||
59 => (10, 3, 4), // k8_8_8_8SScaled
|
||||
60 => (10, 4, 4), // k8_8_8_8UInt
|
||||
61 => (10, 5, 4), // k8_8_8_8SInt
|
||||
62 => (11, 4, 2), // k32_32UInt
|
||||
63 => (11, 5, 2), // k32_32SInt
|
||||
64 => (11, 7, 2), // k32_32Float
|
||||
65 => (12, 0, 4), // k16_16_16_16UNorm
|
||||
66 => (12, 1, 4), // k16_16_16_16SNorm
|
||||
67 => (12, 2, 4), // k16_16_16_16UScaled
|
||||
68 => (12, 3, 4), // k16_16_16_16SScaled
|
||||
69 => (12, 4, 4), // k16_16_16_16UInt
|
||||
70 => (12, 5, 4), // k16_16_16_16SInt
|
||||
71 => (12, 7, 4), // k16_16_16_16Float
|
||||
72 => (13, 4, 3), // k32_32_32UInt
|
||||
73 => (13, 5, 3), // k32_32_32SInt
|
||||
74 => (13, 7, 3), // k32_32_32Float
|
||||
75 => (14, 4, 4), // k32_32_32_32UInt
|
||||
76 => (14, 5, 4), // k32_32_32_32SInt
|
||||
77 => (14, 7, 4), // k32_32_32_32Float
|
||||
_ => (14, 7, Math.Clamp(fallbackComponents, 1u, 4u)),
|
||||
};
|
||||
}
|
||||
|
||||
private static bool TryReadUInt16(CpuContext ctx, ulong address, out ushort value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[2];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt16LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool TryReadUInt32(CpuContext ctx, ulong address, out uint value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[4];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt32LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
|
||||
private static bool TryReadUInt64(CpuContext ctx, ulong address, out ulong value)
|
||||
{
|
||||
Span<byte> buffer = stackalloc byte[8];
|
||||
if (!ctx.Memory.TryRead(address, buffer))
|
||||
{
|
||||
value = 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
value = System.Buffers.Binary.BinaryPrimitives.ReadUInt64LittleEndian(buffer);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -12,7 +12,7 @@ internal enum DetileEquation
|
||||
/// <summary>Unsupported mode/format; caller must use the CPU path or raw upload.</summary>
|
||||
None,
|
||||
|
||||
/// <summary>Exact AddrLib XOR equation (RDNA2 modes 5/9/24/27): factored X/Y terms.</summary>
|
||||
/// <summary>Exact AddrLib XOR equation (RDNA2 modes 1/5/9/24/27): factored X/Y terms.</summary>
|
||||
ExactXor,
|
||||
|
||||
/// <summary>Other modes: a precomputed in-block Morton/standard element-offset table.</summary>
|
||||
@@ -145,6 +145,18 @@ internal static unsafe class GnmTiling
|
||||
Y(2), X(2), Y(3), X(3), Y(4), X(4), Y(5), X(5)],
|
||||
];
|
||||
|
||||
// GFX10 256B_S: 8-bit micro-tile equation (low octet of the 4K_S pattern).
|
||||
// The generic StandardSwizzle bit-interleave is a different layout and leaves
|
||||
// a broken grid on Gen5 UI atlases that ship as Standard256B.
|
||||
private static readonly AddressBit[][] Standard256 =
|
||||
[
|
||||
[X(0), X(1), X(2), X(3), Y(0), Y(1), Y(2), Y(3)],
|
||||
[Zero, X(0), X(1), X(2), Y(0), Y(1), Y(2), X(3)],
|
||||
[Zero, Zero, X(0), X(1), Y(0), Y(1), Y(2), X(2)],
|
||||
[Zero, Zero, Zero, X(0), Y(0), Y(1), X(1), X(2)],
|
||||
[Zero, Zero, Zero, Zero, Y(0), Y(1), X(0), X(1)],
|
||||
];
|
||||
|
||||
// GFX10 4K_S has a separate 12-bit micro-tile equation. It is not the
|
||||
// generic x/y interleave used by the 64K standard block; using that larger
|
||||
// equation leaves a regular grid in linearized atlases.
|
||||
@@ -789,6 +801,7 @@ internal static unsafe class GnmTiling
|
||||
|
||||
pattern = swizzleMode switch
|
||||
{
|
||||
1 => Standard256[bytesPerElementLog2],
|
||||
5 => Standard4K[bytesPerElementLog2],
|
||||
9 => RbPlus64KStandard[bytesPerElementLog2],
|
||||
24 => RbPlus64KDepthX[bytesPerElementLog2],
|
||||
|
||||
@@ -1,6 +1,8 @@
|
||||
// Copyright (C) 2026 SharpEmu Emulator Project
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
using System.Diagnostics;
|
||||
|
||||
namespace SharpEmu.Libs.Agc;
|
||||
|
||||
/// <summary>
|
||||
@@ -92,6 +94,64 @@ internal static class GpuWaitRegistry
|
||||
}
|
||||
}
|
||||
|
||||
public readonly record struct OutstandingSnapshot(
|
||||
int Outstanding,
|
||||
int Latched,
|
||||
long OldestAgeMs,
|
||||
ulong SampleWaitAddress,
|
||||
string? SampleQueueName);
|
||||
|
||||
/// <summary>
|
||||
/// Diagnostics snapshot of suspended WAIT_REG_MEM / dims waiters.
|
||||
/// </summary>
|
||||
public static OutstandingSnapshot SnapshotOutstanding(object? memory = null)
|
||||
{
|
||||
lock (_gate)
|
||||
{
|
||||
var outstanding = 0;
|
||||
var latched = 0;
|
||||
var oldestTicks = long.MaxValue;
|
||||
ulong sampleAddress = 0;
|
||||
string? sampleQueue = null;
|
||||
var now = Stopwatch.GetTimestamp();
|
||||
foreach (var (_, list) in _waiters)
|
||||
{
|
||||
foreach (var waiter in list)
|
||||
{
|
||||
if (memory is not null &&
|
||||
!ReferenceEquals(waiter.Memory, memory))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
outstanding++;
|
||||
if (waiter.Latched)
|
||||
{
|
||||
latched++;
|
||||
}
|
||||
|
||||
if (waiter.RegisteredTicks != 0 &&
|
||||
waiter.RegisteredTicks < oldestTicks)
|
||||
{
|
||||
oldestTicks = waiter.RegisteredTicks;
|
||||
sampleAddress = waiter.WaitAddress;
|
||||
sampleQueue = waiter.QueueName;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
var oldestAgeMs = oldestTicks == long.MaxValue || oldestTicks == 0
|
||||
? 0L
|
||||
: (now - oldestTicks) * 1000L / Stopwatch.Frequency;
|
||||
return new OutstandingSnapshot(
|
||||
outstanding,
|
||||
latched,
|
||||
oldestAgeMs,
|
||||
sampleAddress,
|
||||
sampleQueue);
|
||||
}
|
||||
}
|
||||
|
||||
public static void Register(ulong address, WaitingDcb waiter)
|
||||
{
|
||||
waiter.WaitAddress = address;
|
||||
|
||||
Reference in New Issue
Block a user