diff --git a/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.Alu.cs b/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.Alu.cs index 76a054e0..f5a1d521 100644 --- a/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.Alu.cs +++ b/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.Alu.cs @@ -24,6 +24,11 @@ public static partial class Gen5SpirvTranslator return TryEmitVectorCompare(instruction, out error); } + if (instruction.Opcode == "VReadlaneB32") + { + return TryEmitReadlane(instruction, out error); + } + if (!TryGetVectorDestination(instruction, out var destination)) { error = "missing vector destination"; @@ -34,7 +39,6 @@ public static partial class Gen5SpirvTranslator switch (instruction.Opcode) { case "VMovB32": - case "VReadlaneB32": case "VReadfirstlaneB32": result = GetRawSource(instruction, 0); break; @@ -2365,6 +2369,42 @@ public static partial class Gen5SpirvTranslator StoreWaveMask(106, carry); } + private bool TryEmitReadlane( + Gen5ShaderInstruction instruction, + out string error) + { + error = string.Empty; + if (instruction.Destinations.Count == 0 || + instruction.Destinations[0].Kind != Gen5OperandKind.ScalarRegister) + { + error = "VReadlaneB32 expects scalar destination"; + return false; + } + + var destination = instruction.Destinations[0].Value; + var src0 = GetRawSource(instruction, 0); + + if (_subgroupInvocationIdInput != 0) + { + // sdst = vsrc0[lane(src1)] — broadcast from the specified lane. + var laneSelect = GetRawSource(instruction, 1); + var broadcast = _module.AddInstruction( + SpirvOp.GroupNonUniformBroadcast, + _uintType, + UInt(3), // Subgroup scope + src0, + laneSelect); + StoreS(destination, broadcast); + } + else + { + // Fallback: no subgroup ops, read current lane's value. + StoreS(destination, src0); + } + + return true; + } + private uint EmitPermlane16( Gen5ShaderInstruction instruction, bool exchangeRows) diff --git a/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.cs b/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.cs index 34478eec..c2cbebe7 100644 --- a/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.cs +++ b/src/SharpEmu.ShaderCompiler.Vulkan/Gen5SpirvTranslator.cs @@ -2507,7 +2507,7 @@ public static partial class Gen5SpirvTranslator private bool UsesSubgroupShuffle() => _state.Program.Instructions.Any(instruction => - instruction.Opcode is "VPermlane16B32" or "VPermlanex16B32"); + instruction.Opcode is "VPermlane16B32" or "VPermlanex16B32" or "VReadlaneB32"); private bool UsesWaveControl() => _state.Program.Instructions.Any(instruction => diff --git a/src/SharpEmu.ShaderCompiler/Gen5ShaderTranslator.cs b/src/SharpEmu.ShaderCompiler/Gen5ShaderTranslator.cs index c4155bd8..3df3d918 100644 --- a/src/SharpEmu.ShaderCompiler/Gen5ShaderTranslator.cs +++ b/src/SharpEmu.ShaderCompiler/Gen5ShaderTranslator.cs @@ -1467,6 +1467,12 @@ public static class Gen5ShaderTranslator Gen5Operand.Source((extra >> 18) & 0x1FF, literal), ]; destinations = [Gen5Operand.Vector(word & 0xFF)]; + if (opcode == "VReadlaneB32") + { + // VReadlaneB32 writes to scalar destination (bits 8-14), not vector. + // Bits 0-7 are unused for this opcode. + destinations = [Gen5Operand.Scalar((word >> 8) & 0x7F)]; + } var isVop3B = IsVop3BOpcode((word >> 16) & 0x3FF); control = new Gen5Vop3Control( isVop3B ? 0 : (word >> 8) & 0x7,