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VMovrelsB32 opcode fix (#825)
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Astell
@@ -0,0 +1,210 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.ShaderCompiler;
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using SharpEmu.ShaderCompiler.Vulkan;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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// Regression tests for the VOP1 register-relative moves V_MOVRELD_B32 /
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// V_MOVRELS_B32 / V_MOVRELSD_B32 / V_MOVRELSD_2_B32 (opcodes 0x42/0x43/0x44/
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// 0x48). These add M0 at run time to the source and/or destination register
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// number encoded in the instruction, which is how a shader compiler implements
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// a dynamically indexed array that stayed in registers. The decoder named them
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// but nothing lowered them, so they hit the vector-ALU switch default and failed
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// emission ("unsupported vector opcode"), dropping the whole shader — Astro Bot
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// ships pixel shaders that use V_MOVRELS_B32.
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//
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// The register file is a private uint array, so the lowering is an OpAccessChain
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// with a computed (non-constant) index. Each test therefore asserts both that
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// the shader survives translation and that the relative operand really became a
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// dynamic index rather than a constant one.
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public sealed class Gen5MoveRelativeSpirvTests
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{
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private const ulong ShaderAddress = 0x1_0000_0000;
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// VOP1: [31:25]=0b0111111, [24:17]=vdst, [16:9]=op, [8:0]=src0
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// (src0 >= 256 selects a VGPR).
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private const uint Vop1 = 0x7E000000;
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// SOP1 s_mov_b32 m0, <inline 2>: [31:23]=0b101111101, [22:16]=sdst,
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// [15:8]=op(0x03), [7:0]=ssrc0. m0 is SGPR 124, inline constant 2 is 130.
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private const uint SMovM0 = 0xBE800000u | (124u << 16) | (0x03u << 8) | 130u;
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[Fact]
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public void MovrelsB32_ReadsTheSourceRegisterThroughADynamicIndex()
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{
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// s_mov_b32 m0, 2 ; v_movrels_b32 v5, v3 -> v5 = vgpr[3 + m0]
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var spirv = Compile([SMovM0, Vop1 | (5u << 17) | (0x43u << 9) | (256u + 3u)]);
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Assert.True(
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HasDynamicVectorRegisterAccess(spirv),
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"V_MOVRELS_B32 must index the VGPR array with a computed index");
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}
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[Fact]
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public void MovreldB32_WritesTheDestinationRegisterThroughADynamicIndex()
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{
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// s_mov_b32 m0, 2 ; v_movreld_b32 v5, v3 -> vgpr[5 + m0] = v3
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var spirv = Compile([SMovM0, Vop1 | (5u << 17) | (0x42u << 9) | (256u + 3u)]);
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Assert.True(
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HasDynamicVectorRegisterAccess(spirv),
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"V_MOVRELD_B32 must index the VGPR array with a computed index");
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}
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[Fact]
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public void MovrelsdB32_TranslatesWithoutDroppingShader()
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{
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// s_mov_b32 m0, 2 ; v_movrelsd_b32 v5, v3 -> vgpr[5 + m0] = vgpr[3 + m0]
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var spirv = Compile([SMovM0, Vop1 | (5u << 17) | (0x44u << 9) | (256u + 3u)]);
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Assert.True(
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HasDynamicVectorRegisterAccess(spirv),
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"V_MOVRELSD_B32 must index the VGPR array with a computed index");
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}
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[Fact]
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public void Movrelsd2B32_TranslatesWithoutDroppingShader()
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{
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// s_mov_b32 m0, 2 ; v_movrelsd_2_b32 v5, v3, which splits m0 into two
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// 10-bit halves (source index in [9:0], destination index in [25:16]).
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var spirv = Compile([SMovM0, Vop1 | (5u << 17) | (0x48u << 9) | (256u + 3u)]);
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Assert.True(
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HasDynamicVectorRegisterAccess(spirv),
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"V_MOVRELSD_2_B32 must index the VGPR array with a computed index");
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}
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[Fact]
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public void MovrelsB32_RejectsANonVectorSource()
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{
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// v_movrels_b32 v5, s3. The relative source is architecturally a VGPR;
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// an SGPR encoding is malformed and must fail translation rather than
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// silently read the wrong register file.
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Assert.False(
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TryCompile(
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[SMovM0, Vop1 | (5u << 17) | (0x43u << 9) | 3u],
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out _,
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out var error));
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Assert.Contains("vector register", error, StringComparison.Ordinal);
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}
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// True when some OpAccessChain into the "vgpr" array uses an index that is
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// not an OpConstant — i.e. a register number computed from M0.
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private static bool HasDynamicVectorRegisterAccess(byte[] spirv)
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{
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var vectorRegisters = FindNamedId(spirv, "vgpr");
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Assert.True(vectorRegisters != 0, "the module must name its VGPR array");
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var constants = new HashSet<uint>();
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foreach (var (op, wordCount, offset) in EnumerateInstructions(spirv))
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{
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// OpConstant = 43, OpConstantNull = 46: (opcode, resultType, resultId, ...).
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if (op is 43 or 46 && wordCount >= 3)
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{
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constants.Add(ReadWord(spirv, offset + 8));
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}
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}
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foreach (var (op, wordCount, offset) in EnumerateInstructions(spirv))
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{
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// OpAccessChain = 65: (opcode, resultType, resultId, base, index...).
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if (op != 65 || wordCount < 5 || ReadWord(spirv, offset + 12) != vectorRegisters)
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{
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continue;
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}
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if (!constants.Contains(ReadWord(spirv, offset + 16)))
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{
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return true;
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}
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}
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return false;
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}
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// Result id of the OpName whose literal string matches, or 0.
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private static uint FindNamedId(byte[] spirv, string name)
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{
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foreach (var (op, wordCount, offset) in EnumerateInstructions(spirv))
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{
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// OpName = 5: (opcode, target, literal string...).
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if (op != 5 || wordCount < 3)
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{
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continue;
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}
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var bytes = spirv.AsSpan(offset + 8, (wordCount - 2) * sizeof(uint));
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var terminator = bytes.IndexOf((byte)0);
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var text = System.Text.Encoding.UTF8.GetString(
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terminator < 0 ? bytes : bytes[..terminator]);
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if (text == name)
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{
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return ReadWord(spirv, offset + 4);
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}
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}
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return 0;
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}
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private static IEnumerable<(ushort Op, int WordCount, int Offset)> EnumerateInstructions(
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byte[] spirv)
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{
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// 5-word SPIR-V header, then (wordCount << 16 | opcode) packed instructions.
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for (var offset = 5 * sizeof(uint); offset + sizeof(uint) <= spirv.Length;)
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{
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var word = ReadWord(spirv, offset);
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var wordCount = (int)(word >> 16);
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if (wordCount <= 0)
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{
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yield break;
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}
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yield return ((ushort)word, wordCount, offset);
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offset += wordCount * sizeof(uint);
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}
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}
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private static uint ReadWord(byte[] spirv, int offset) =>
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BinaryPrimitives.ReadUInt32LittleEndian(spirv.AsSpan(offset, sizeof(uint)));
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private static byte[] Compile(uint[] programWords)
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{
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Assert.True(TryCompile(programWords, out var spirv, out var error), error);
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return spirv;
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}
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private static bool TryCompile(uint[] programWords, out byte[] spirv, out string error)
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{
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spirv = [];
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var memory = new FakeCpuMemory(ShaderAddress, 0x2000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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Gen5ShaderAtomicDecodeTests.WriteProgram(memory, ShaderAddress, programWords);
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var shaderRegisters = new Dictionary<uint, uint>
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{
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[Gen5ShaderAtomicDecodeTests.ComputePgmRsrc2Register] = 16u << 1,
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};
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if (!Gen5ShaderTranslator.TryCreateState(
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ctx,
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ShaderAddress,
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0,
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shaderRegisters,
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Gen5ShaderAtomicDecodeTests.ComputeUserDataRegister,
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out var state,
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out error) ||
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!Gen5ShaderScalarEvaluator.TryEvaluate(ctx, state, out var evaluation, out error) ||
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!Gen5SpirvTranslator.TryCompileComputeShader(
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state, evaluation, 1, 1, 1, out var shader, out error))
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{
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return false;
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}
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spirv = shader.Spirv;
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return true;
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}
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}
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