feat(gpu): GPU compute detile for guest tiled textures (Vulkan + Metal) (#592)

* feat(gpu): GPU compute detile for guest tiled textures (Vulkan + Metal) Move RDNA2 exact-XOR deswizzle (swizzle modes 5/9/24/27, 4bpp) off the CPU onto a GPU compute pass. GnmTiling.GetDetileParams resolves the shared addressing into DetileParams; the CPU fallback and both GPU kernels consume the same params so they never disagree. Vulkan (verified bit-exact on NVIDIA): SpirvFixedShaders.CreateDetileCompute hand-emits the SPIR-V kernel; VulkanDetilePass.RecordDetile records the dispatch into the async batch command buffer (never a blocking submit on the render thread) with transients retired via fence; VulkanDetileSelfTest (SHARPEMU_DETILE_SELFTEST=1) checks both entry points against the CPU detile. Metal (Mac-untested): detile_compute.msl (detile_cs) + MetalDetilePass mirror the Vulkan pass. The active Metal path CPU-detiles via the new GnmTiling.DetileWithParams when a texture arrives packaged (empty RgbaPixels + TiledSource/Detile), keeping Metal correct under default-on with no regression; wiring MetalDetilePass live is the remaining on-device step. Flags: GPU detile is default-on (SHARPEMU_GPU_DETILE=0 disables); [GPU-DETILE] diagnostics gated behind SHARPEMU_LOG_GPU_DETILE=1. Tests: 17 detile unit tests pass, incl. DetileWithParams and GetDetileParams each matching TryDetile bit-for-bit across all supported modes/bpp, plus a SPIR-V structural-validity test. * feat(gpu): GPU compute detile for guest tiled textures (Vulkan + Metal) Move RDNA2 exact-XOR deswizzle (swizzle modes 5/9/24/27, 4bpp) off the CPU onto a GPU compute pass. GnmTiling.GetDetileParams resolves the shared addressing into DetileParams that the CPU fallback and both GPU kernels consume, so they never disagree; everything else keeps the CPU path. Vulkan (verified bit-exact on NVIDIA): SpirvFixedShaders.CreateDetileCompute hand-emits the kernel; VulkanDetilePass.RecordDetile records into the async batch command buffer (never a blocking submit on the render thread) with transients retired via fence, falling back to CPU detile on failure. VulkanDetileSelfTest (SHARPEMU_DETILE_SELFTEST=1) checks both entry points. Metal (Mac-untested): detile_compute.msl + MetalDetilePass mirror the Vulkan pass; the active Metal path CPU-detiles via GnmTiling.DetileWithParams so it stays correct under default-on. Wiring MetalDetilePass live is a follow-up. Flags: default-on (SHARPEMU_GPU_DETILE=0 disables); diagnostics behind SHARPEMU_LOG_GPU_DETILE=1. Adds 17 passing detile unit tests. * Fix: added support layered texture support for the GPU-Detiling. * Fix: Added support for BlockTable (1 / 4 / 8 (Morton/Z-order)) * feat: added support for 8 and 16 bpp (bytes per element) * Fixed a build failure specific to this branch ---------
2026-07-31 15:09:42 +08:00 · 2026-07-24 19:13:02 +02:00
parent 5228335f15
commit a158960c20
13 changed files with 2702 additions and 27 deletions
@@ -76,6 +76,14 @@ public static class MslFixedShaders
    /// </summary>
    public static string CreateDepthOnlyFragment() => MslTemplates.Render("depth_only_fragment");

+    /// <summary>
+    /// Compute kernel that deswizzles one RDNA2 exact-XOR tiled surface (swizzle
+    /// modes 5/9/24/27) at 4 bytes/element into a linear output buffer — the MSL
+    /// twin of <c>SpirvFixedShaders.CreateDetileCompute</c>. Entry point
+    /// "detile_cs"; buffers 0=tiled, 1=xTerm, 2=yTerm, 3=out, 4=DetileParams.
+    /// </summary>
+    public static string CreateDetileCompute() => MslTemplates.Render("detile_compute");
+
    private static string Format(float value) =>
        value.ToString("0.0######", CultureInfo.InvariantCulture) + "f";
 }
@@ -0,0 +1,70 @@
+#include <metal_stdlib>
+
+using namespace metal;
+
+// GPU deswizzle for RDNA2 tiled surfaces at 4/8/16 bytes/element — the MSL twin of
+// SpirvFixedShaders.CreateDetileCompute and a direct mirror of
+// GnmTiling.GetDetileParams. Handles both supported equation families and both
+// plain 2D textures and array textures (one grid-Z layer per slice; the caller
+// packs the tiled slices contiguously). width/height are ELEMENT dims (for
+// block-compressed formats a 4x4 block is one element); each element spans
+// uintsPerElement = bpp/4 words, and the X grid is widened by that factor so each
+// thread copies one word (elemX = gidX / upe, word = gidX % upe):
+//   inBlock = equation == 1  // BlockTable, modes 1/4/8
+//             ? blockTable[(y % blockHeight) * blockWidth + (elemX % blockWidth)]
+//             : xTerm[elemX & xMask] ^ yTerm[y & yMask];   // ExactXor 5/9/24/27
+//   srcElem = z * srcSliceElements
+//           + (y / blockHeight * blocksPerRow + elemX / blockWidth) * blockElements
+//           + inBlock;
+//   dstElem = z * width * height + y * width + elemX;
+//   out[dstElem * upe + word] = tiled[srcElem * upe + word];
+// Term tables hold ELEMENT offsets. buffer(1) carries xTerm (ExactXor) OR the
+// block table (BlockTable); the two equations index different-sized buffers, so
+// exactly one branch runs. 1/2 bpp are sub-word and stay on the CPU.
+struct DetileParams
+{
+    uint width;
+    uint height;
+    uint blockWidth;
+    uint blockHeight;
+    uint blockElements;
+    uint blocksPerRow;
+    uint xMask;
+    uint yMask;
+    uint srcSliceElements;
+    uint equation;
+    uint uintsPerElement;
+};
+
+kernel void detile_cs(
+    device const uint* tiled        [[buffer(0)]],
+    device const uint* xTermOrTable [[buffer(1)]],
+    device const uint* yTerm        [[buffer(2)]],
+    device uint* outLinear          [[buffer(3)]],
+    constant DetileParams& params   [[buffer(4)]],
+    uint3 gid                       [[thread_position_in_grid]])
+{
+    uint elemX = gid.x / params.uintsPerElement;
+    uint word = gid.x - elemX * params.uintsPerElement;
+    if (elemX >= params.width || gid.y >= params.height)
+    {
+        return;
+    }
+
+    uint blockIndex = (gid.y / params.blockHeight) * params.blocksPerRow + (elemX / params.blockWidth);
+    uint off;
+    if (params.equation != 0u)
+    {
+        uint inX = elemX - (elemX / params.blockWidth) * params.blockWidth;
+        uint inY = gid.y - (gid.y / params.blockHeight) * params.blockHeight;
+        off = xTermOrTable[inY * params.blockWidth + inX];
+    }
+    else
+    {
+        off = xTermOrTable[elemX & params.xMask] ^ yTerm[gid.y & params.yMask];
+    }
+
+    uint srcElem = gid.z * params.srcSliceElements + blockIndex * params.blockElements + off;
+    uint dstElem = gid.z * params.width * params.height + gid.y * params.width + elemX;
+    outLinear[dstElem * params.uintsPerElement + word] = tiled[srcElem * params.uintsPerElement + word];
+}