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[AGC] Implement RDNA2 buffer/image/DS 32-bit atomic instructions (#222)
Adds decode and SPIR-V translation for the missing MUBUF, MIMG and DS atomic instructions in the Gen5 shader translator, generalizing the existing BufferAtomicAdd path. Covers swap, cmpswap, add, sub, smin/smax, umin/umax, and/or/xor, inc and dec, plus the DS RTN variants. Image atomics go through OpImageTexelPointer on the storage image binding. Notable: DS_CMPST operand order (DATA0 = comparator, DATA1 = new value) is reversed relative to buffer/image cmpswap, which a dedicated test locks in. ATOMIC_INC/DEC are approximated with OpAtomicIIncrement/IDecrement, exact for the common 0xFFFFFFFF clamp. Verified with 9 new synthetic decoder and end-to-end SPIR-V tests (part of the #36 test corpus effort); full suite passes 35/35. Signed-off-by: missatjuhvdk1 <177474143+missatjuhvdk1@users.noreply.github.com> Co-authored-by: missatjuhvdk1 <177474143+missatjuhvdk1@users.noreply.github.com>
This commit is contained in:
Mees van den Kieboom
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GitHub
GitHub
parent
f2d9051358
commit
9883a9445d
@@ -1172,9 +1172,33 @@ public static class Gen5ShaderTranslator
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name = opcode switch
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{
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0x00 => "DsAddU32",
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0x01 => "DsSubU32",
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0x03 => "DsIncU32",
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0x04 => "DsDecU32",
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0x05 => "DsMinI32",
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0x06 => "DsMaxI32",
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0x07 => "DsMinU32",
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0x08 => "DsMaxU32",
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0x09 => "DsAndB32",
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0x0A => "DsOrB32",
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0x0B => "DsXorB32",
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0x0D => "DsWriteB32",
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0x0E => "DsWrite2B32",
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0x0F => "DsWrite2St64B32",
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0x10 => "DsCmpstB32",
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0x20 => "DsAddRtnU32",
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0x21 => "DsSubRtnU32",
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0x23 => "DsIncRtnU32",
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0x24 => "DsDecRtnU32",
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0x25 => "DsMinRtnI32",
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0x26 => "DsMaxRtnI32",
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0x27 => "DsMinRtnU32",
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0x28 => "DsMaxRtnU32",
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0x29 => "DsAndRtnB32",
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0x2A => "DsOrRtnB32",
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0x2B => "DsXorRtnB32",
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0x2D => "DsWrxchgRtnB32",
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0x30 => "DsCmpstRtnB32",
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0x35 => "DsSwizzleB32",
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0x36 => "DsReadB32",
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0x37 => "DsRead2B32",
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@@ -1272,8 +1296,19 @@ public static class Gen5ShaderTranslator
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0x23 => "BufferLoadSbyteD16Hi",
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0x24 => "BufferLoadShortD16",
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0x25 => "BufferLoadShortD16Hi",
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0x30 => "BufferAtomicSwap",
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0x31 => "BufferAtomicCmpswap",
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0x32 => "BufferAtomicAdd",
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0x38 => "BufferAtomicUMax",
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0x33 => "BufferAtomicSub",
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0x35 => "BufferAtomicSmin",
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0x36 => "BufferAtomicUmin",
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0x37 => "BufferAtomicSmax",
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0x38 => "BufferAtomicUmax",
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0x39 => "BufferAtomicAnd",
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0x3A => "BufferAtomicOr",
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0x3B => "BufferAtomicXor",
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0x3C => "BufferAtomicInc",
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0x3D => "BufferAtomicDec",
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_ => $"MubufRaw{opcode:X2}",
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};
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sizeDwords = (extra >> 24) == 0xFF ? 3u : 2u;
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@@ -1388,7 +1423,18 @@ public static class Gen5ShaderTranslator
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0x08 => "ImageStore",
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0x09 => "ImageStoreMip",
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0x0E => "ImageGetResinfo",
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0x0F => "ImageAtomicSwap",
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0x10 => "ImageAtomicCmpswap",
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0x11 => "ImageAtomicAdd",
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0x12 => "ImageAtomicSub",
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0x14 => "ImageAtomicSmin",
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0x15 => "ImageAtomicUmin",
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0x16 => "ImageAtomicSmax",
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0x17 => "ImageAtomicUmax",
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0x18 => "ImageAtomicAnd",
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0x19 => "ImageAtomicOr",
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0x1A => "ImageAtomicXor",
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0x1B => "ImageAtomicInc",
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0x1C => "ImageAtomicDec",
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0x20 => "ImageSample",
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0x22 => "ImageSampleD",
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@@ -1488,6 +1534,18 @@ public static class Gen5ShaderTranslator
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name.StartsWith("ImageStore", StringComparison.Ordinal) ||
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name.StartsWith("ImageAtomic", StringComparison.Ordinal);
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public static bool IsDataShareAtomic(string name) => name switch
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{
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"DsAddU32" or "DsSubU32" or "DsIncU32" or "DsDecU32" or
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"DsMinI32" or "DsMaxI32" or "DsMinU32" or "DsMaxU32" or
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"DsAndB32" or "DsOrB32" or "DsXorB32" or "DsCmpstB32" or
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"DsAddRtnU32" or "DsSubRtnU32" or "DsIncRtnU32" or "DsDecRtnU32" or
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"DsMinRtnI32" or "DsMaxRtnI32" or "DsMinRtnU32" or "DsMaxRtnU32" or
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"DsAndRtnB32" or "DsOrRtnB32" or "DsXorRtnB32" or
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"DsWrxchgRtnB32" or "DsCmpstRtnB32" => true,
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_ => false,
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};
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private static Gen5ShaderInstruction CreateInstruction(
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uint pc,
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Gen5ShaderEncoding encoding,
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@@ -1794,10 +1852,6 @@ public static class Gen5ShaderTranslator
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((word >> 17) & 1) != 0);
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sources = opcode switch
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{
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"DsAddU32" => [
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Gen5Operand.Vector(vectorAddress),
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Gen5Operand.Vector(vectorData0),
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],
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"DsWriteB32" => [
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Gen5Operand.Vector(vectorAddress),
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Gen5Operand.Vector(vectorData0),
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@@ -1826,6 +1880,17 @@ public static class Gen5ShaderTranslator
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Gen5Operand.Vector(vectorData1),
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],
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"DsSwizzleB32" => [Gen5Operand.Vector(vectorData0)],
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// DS_CMPST operand order is reversed vs buffer/image cmpswap:
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// DATA0 holds the comparator, DATA1 holds the new value.
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"DsCmpstB32" or "DsCmpstRtnB32" => [
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Gen5Operand.Vector(vectorAddress),
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Gen5Operand.Vector(vectorData0),
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Gen5Operand.Vector(vectorData1),
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],
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_ when IsDataShareAtomic(opcode) => [
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Gen5Operand.Vector(vectorAddress),
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Gen5Operand.Vector(vectorData0),
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],
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_ => [Gen5Operand.Vector(vectorAddress)],
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};
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destinations = opcode switch
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@@ -1848,6 +1913,10 @@ public static class Gen5ShaderTranslator
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Gen5Operand.Vector(vectorDestination + 2),
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Gen5Operand.Vector(vectorDestination + 3),
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],
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_ when IsDataShareAtomic(opcode) &&
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opcode.Contains("Rtn", StringComparison.Ordinal) => [
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Gen5Operand.Vector(vectorDestination),
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],
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_ => [],
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};
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break;
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@@ -1953,8 +2022,8 @@ public static class Gen5ShaderTranslator
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"BufferStoreDwordx2" => 2u,
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"BufferStoreDwordx3" => 3u,
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"BufferStoreDwordx4" => 4u,
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"BufferAtomicAdd" => 1u,
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"BufferAtomicUMax" => 1u,
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"BufferAtomicCmpswap" => 2u,
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_ when opcode.StartsWith("BufferAtomic", StringComparison.Ordinal) => 1u,
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_ => 0u,
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};
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sources =
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