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[AGC] Decode VOP3P and emit packed f16 arithmetic (first slice) (#145)
* [AGC] Decode VOP3P and emit packed f16 arithmetic (first slice) On gfx10 the VOP3P family lives under its own 0b110011000 prefix (word0 top byte 0xCC), which the major-opcode switch currently routes to the SMEM branch, so packed instructions were decoded as scalar memory ops and emitted as silent no-ops. Intercept the exact 9-bit prefix ahead of the switch, decode the five packed-f16 arithmetic opcodes with their op_sel/op_sel_hi/neg_lo/neg_hi/clamp modifiers, and emit them as UnpackHalf2x16 -> component-wise f32 vec2 ops -> PackHalf2x16 so no Float16 capability is needed. Bit layout and opcode numbers pinned to LLVM MC test encodings (vop3p.s, gfx10_vop3p_literalv216.txt) and VOP3PInstructions.td. Unsupported modifiers, packed constants and out-of-scope packed opcodes fail with a clear error instead of emitting wrong results. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> * [AGC] Make packed f16 exact and drop v_pk_fma_f16 (review response) Address the FP16 correctness review on the VOP3P slice. Replace GLSL UnpackHalf2x16/PackHalf2x16 with explicit integer f16<->f32 conversions (EmitHalfToFloat/EmitFloatToHalf): exact widening with subnormal normalisation, and narrowing with round-to-nearest-even, overflow-to-Inf and NaN/Inf handling. Their subnormal and rounding behaviour no longer depends on implementation-defined float-controls modes. With exact conversions, v_pk_add_f16 and v_pk_mul_f16 are bit-exact to a true f16 op (f32 result rounds losslessly to f16; a f16 product fits in f32). Emit v_pk_min_f16/v_pk_max_f16 as fminnum_like/fmaxnum_like (NaN operand returns the other; ordered numeric compare) instead of GLSL FMin/FMax. v_pk_fma_f16 now fails emission loudly: a fused f16 FMA rounds once, an f32 multiply-add then pack double-rounds (fma(0x4100,0x7522,0x04EA) is 0x7A6B fused vs 0x7A6A via f32). Exact fused emulation is a planned follow-up slice. ShaderDump gains an Expect model (Translates/DecodeFails/EmitFails) and packed regressions: arith, non-default modifiers, and loud-failure pins for the fma case above and for clamp. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> --------- Co-authored-by: tensorcrush <tensorcrush@users.noreply.github.com> Co-authored-by: Claude Fable 5 <noreply@anthropic.com> Co-authored-by: Antigravity AI <antigravity@gemini.com>
This commit is contained in:
tensorcrush
@@ -948,6 +948,27 @@ public static partial class Gen5SpirvTranslator
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vector);
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break;
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}
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case "VPkAddF16":
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case "VPkMulF16":
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case "VPkMinF16":
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case "VPkMaxF16":
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if (!TryEmitPackedF16(instruction, out result, out error))
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{
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return false;
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}
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break;
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case "VPkFmaF16":
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// Deliberately loud: a fused f16 FMA rounds the product+add once,
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// whereas doing the multiply-add in f32 and rounding to f16 at the
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// end double-rounds. Concrete miss: fma(0x4100, 0x7522, 0x04EA) is
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// 0x7A6B fused but 0x7A6A via f32. Exact emulation (round-to-odd
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// f32 product then RNE pack) is a planned follow-up slice.
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error =
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$"unsupported vop3p opcode {instruction.Opcode} " +
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"(fused f16 FMA requires single-rounding; deferred to a later slice)";
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return false;
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default:
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error = $"unsupported vector opcode {instruction.Opcode}";
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return false;
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@@ -976,6 +997,213 @@ public static partial class Gen5SpirvTranslator
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return true;
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}
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// Packed f16 (VOP3P) arithmetic. Each source register holds two f16 values,
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// one per result lane. Every f16<->f32 conversion is done with the explicit
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// integer sequences below (EmitHalfToFloat / EmitFloatToHalf) instead of
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// GLSL UnpackHalf2x16 / PackHalf2x16, whose subnormal and rounding behaviour
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// is implementation-defined without float-controls execution modes. The two
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// lanes are computed independently: each operand half is widened exactly to
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// f32, op_sel/op_sel_hi pick the source half and neg_lo/neg_hi negate it, the
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// op runs in f32, and the result is rounded back to f16 with round-to-nearest-
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// even. For add and mul this is bit-exact to a true f16 op (the f32 result
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// rounds losslessly to f16 by the double-rounding theorem; a f16 product even
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// fits in f32 exactly). min/max carry no rounding, so they are exact once the
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// conversions are. v_pk_fma_f16 is intentionally not routed here because a
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// fused f16 FMA cannot be reproduced by an f32 multiply-add plus a pack.
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private bool TryEmitPackedF16(
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Gen5ShaderInstruction instruction,
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out uint result,
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out string error)
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{
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result = 0;
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error = string.Empty;
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if (instruction.Control is not Gen5Vop3pControl control)
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{
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error = $"missing vop3p control for {instruction.Opcode}";
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return false;
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}
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if (control.Clamp)
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{
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error = $"unsupported vop3p modifiers (clamp) for {instruction.Opcode}";
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return false;
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}
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for (var index = 0; index < 2; index++)
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{
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var source = instruction.Sources[index];
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if (source.Kind is not (Gen5OperandKind.VectorRegister or Gen5OperandKind.ScalarRegister))
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{
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error =
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$"unsupported vop3p operand {source} for {instruction.Opcode} (first slice: registers only)";
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return false;
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}
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}
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var low = EmitPackedF16Lane(instruction, control, highLane: false);
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var high = EmitPackedF16Lane(instruction, control, highLane: true);
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result = BitwiseOr(low, ShiftLeftLogical(high, UInt(16)));
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return true;
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}
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// Computes one result lane (low or high) as a packed 16-bit f16 value.
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private uint EmitPackedF16Lane(
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Gen5ShaderInstruction instruction,
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Gen5Vop3pControl control,
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bool highLane)
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{
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var left = EmitPackedF16Operand(instruction, control, 0, highLane);
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var right = EmitPackedF16Operand(instruction, control, 1, highLane);
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var value = instruction.Opcode switch
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{
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"VPkAddF16" => _module.AddInstruction(SpirvOp.FAdd, _floatType, left, right),
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"VPkMulF16" => _module.AddInstruction(SpirvOp.FMul, _floatType, left, right),
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"VPkMinF16" => EmitPackedF16MinMax(left, right, isMax: false),
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"VPkMaxF16" => EmitPackedF16MinMax(left, right, isMax: true),
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_ => left,
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};
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return EmitFloatToHalf(Bitcast(_uintType, value));
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}
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// Reads source `index`, selects the half feeding this lane (op_sel / op_sel_hi),
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// widens it exactly to f32 and applies the lane's negate modifier (neg_lo / neg_hi).
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private uint EmitPackedF16Operand(
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Gen5ShaderInstruction instruction,
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Gen5Vop3pControl control,
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int index,
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bool highLane)
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{
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var raw = GetRawSource(instruction, index);
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var selectMask = highLane ? control.OpSelHiMask : control.OpSelMask;
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var half = ((selectMask >> index) & 1) != 0
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? ShiftRightLogical(raw, UInt(16))
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: raw;
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var value = Bitcast(_floatType, EmitHalfToFloat(half));
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var negateMask = highLane ? control.NegHiMask : control.NegLoMask;
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if (((negateMask >> index) & 1) != 0)
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{
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value = _module.AddInstruction(SpirvOp.FNegate, _floatType, value);
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}
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return value;
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}
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// fminnum_like / fmaxnum_like: if one operand is NaN return the other; if both
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// are NaN return a NaN; otherwise the ordered smaller/larger. The ordering of
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// -0/+0 is unspecified under these opcodes, so the ordered compare is enough.
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private uint EmitPackedF16MinMax(uint left, uint right, bool isMax)
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{
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var compare = _module.AddInstruction(
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isMax ? SpirvOp.FOrdGreaterThan : SpirvOp.FOrdLessThan,
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_boolType,
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left,
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right);
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var numeric = _module.AddInstruction(
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SpirvOp.Select, _floatType, compare, left, right);
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var leftNan = _module.AddInstruction(SpirvOp.IsNan, _boolType, left);
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var rightNan = _module.AddInstruction(SpirvOp.IsNan, _boolType, right);
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var withRight = _module.AddInstruction(
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SpirvOp.Select, _floatType, rightNan, left, numeric);
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return _module.AddInstruction(
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SpirvOp.Select, _floatType, leftNan, right, withRight);
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}
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// Widens an f16 value held in the low 16 bits of `halfBits` to an f32 bit
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// pattern, exactly (subnormals normalised, Inf/NaN and signed zero preserved).
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// Mirrors the branchless HalfToFloat reference validated against System.Half.
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private uint EmitHalfToFloat(uint halfBits)
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{
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var sign = ShiftLeftLogical(BitwiseAnd(halfBits, UInt(0x8000)), UInt(16));
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var exponent = BitwiseAnd(ShiftRightLogical(halfBits, UInt(10)), UInt(0x1F));
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var mantissa = BitwiseAnd(halfBits, UInt(0x3FF));
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var normal = BitwiseOr(
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ShiftLeftLogical(IAdd(exponent, UInt(112)), UInt(23)),
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ShiftLeftLogical(mantissa, UInt(13)));
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var infinityNan = BitwiseOr(UInt(0x7F80_0000), ShiftLeftLogical(mantissa, UInt(13)));
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// Subnormal: normalise the mantissa. FindUMsb of (mantissa | 1) keeps the
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// op defined when mantissa is 0; that lane is discarded by the select below.
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var highBit = Ext(75, _uintType, BitwiseOr(mantissa, UInt(1)));
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var shift = ISubU(UInt(23), highBit);
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var subFraction = BitwiseAnd(ShiftLeftLogical(mantissa, shift), UInt(0x7F_FFFF));
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var subnormal = SelectU(
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IsNotZero(mantissa),
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BitwiseOr(ShiftLeftLogical(IAdd(highBit, UInt(103)), UInt(23)), subFraction),
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UInt(0));
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var magnitude = SelectU(
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Equal(exponent, 0),
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subnormal,
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SelectU(Equal(exponent, 31), infinityNan, normal));
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return BitwiseOr(sign, magnitude);
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}
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// Narrows an f32 bit pattern to an f16 value in the low 16 bits, rounding to
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// nearest even (subnormals, overflow-to-Inf and NaN/Inf handled). Mirrors the
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// branchless FloatToHalf reference validated exhaustively against System.Half.
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private uint EmitFloatToHalf(uint bits)
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{
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var sign = BitwiseAnd(ShiftRightLogical(bits, UInt(16)), UInt(0x8000));
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var absolute = BitwiseAnd(bits, UInt(0x7FFF_FFFF));
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var isInfinityNan = UCmp(SpirvOp.UGreaterThanEqual, absolute, UInt(0x7F80_0000));
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var isNan = UCmp(SpirvOp.UGreaterThan, absolute, UInt(0x7F80_0000));
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var infinityNan = BitwiseOr(
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BitwiseOr(sign, UInt(0x7C00)),
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SelectU(isNan, UInt(0x200), UInt(0)));
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var exponent = ShiftRightLogical(absolute, UInt(23));
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var mantissa = BitwiseAnd(absolute, UInt(0x7F_FFFF));
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var significand = BitwiseOr(mantissa, UInt(0x80_0000));
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// Normal path: round the 24-bit significand down to 11 bits (>> 13) with
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// round-to-nearest-even; the carry folds naturally into the exponent.
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var roundBit = BitwiseAnd(ShiftRightLogical(significand, UInt(13)), UInt(1));
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var rounded = ShiftRightLogical(IAdd(IAdd(significand, UInt(0xFFF)), roundBit), UInt(13));
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var halfExponent = ISubU(exponent, UInt(112));
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var normalBits = IAdd(ShiftLeftLogical(halfExponent, UInt(10)), ISubU(rounded, UInt(0x400)));
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var normal = SelectU(
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UCmp(SpirvOp.UGreaterThanEqual, exponent, UInt(113)),
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SelectU(UCmp(SpirvOp.UGreaterThanEqual, normalBits, UInt(0x7C00)), UInt(0x7C00), normalBits),
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UInt(0));
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// Subnormal path: value = round(significand >> (126 - exponent)) with RNE.
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// The shift is clamped to 25 so it stays defined; on this path it is >= 14.
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var distance = ISubU(UInt(126), exponent);
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var shift = SelectU(UCmp(SpirvOp.UGreaterThan, distance, UInt(25)), UInt(25), distance);
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var shiftMask = ISubU(ShiftLeftLogical(UInt(1), shift), UInt(1));
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var halfWay = ShiftLeftLogical(UInt(1), ISubU(shift, UInt(1)));
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var lowBits = BitwiseAnd(significand, shiftMask);
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var quotient = ShiftRightLogical(significand, shift);
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var roundUp = _module.AddInstruction(
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SpirvOp.LogicalOr,
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_boolType,
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UCmp(SpirvOp.UGreaterThan, lowBits, halfWay),
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_module.AddInstruction(
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SpirvOp.LogicalAnd,
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_boolType,
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Equal(lowBits, halfWay),
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IsNotZero(BitwiseAnd(quotient, UInt(1)))));
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var subnormal = IAdd(quotient, SelectU(roundUp, UInt(1), UInt(0)));
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var isSubnormal = UCmp(SpirvOp.ULessThanEqual, exponent, UInt(112));
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var finite = SelectU(isSubnormal, subnormal, normal);
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return SelectU(isInfinityNan, infinityNan, BitwiseOr(sign, finite));
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}
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private uint SelectU(uint condition, uint whenTrue, uint whenFalse) =>
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_module.AddInstruction(SpirvOp.Select, _uintType, condition, whenTrue, whenFalse);
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private uint UCmp(SpirvOp operation, uint left, uint right) =>
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_module.AddInstruction(operation, _boolType, left, right);
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private uint Equal(uint value, uint constant) =>
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_module.AddInstruction(SpirvOp.IEqual, _boolType, value, UInt(constant));
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private uint ISubU(uint left, uint right) =>
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_module.AddInstruction(SpirvOp.ISub, _uintType, left, right);
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private bool TryEmitVectorCompare(
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Gen5ShaderInstruction instruction,
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out string error)
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