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https://github.com/par274/sharpemu.git
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revert: restore state before huge regression
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ParantezTech
@@ -1,293 +0,0 @@
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// Copyright (C) 2026 SharpEmu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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using System.Buffers.Binary;
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using SharpEmu.HLE;
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using SharpEmu.Libs.Agc;
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using SharpEmu.ShaderCompiler;
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using Xunit;
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namespace SharpEmu.Libs.Tests.Agc;
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/// <summary>
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/// Coverage for AGC attrib-table → BufferFormat merge and semantic indexing.
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/// </summary>
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public sealed class AgcVertexMetadataTests
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{
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[Fact]
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public void BuildVertexResources_UsesSemanticNotHardwareMappingAsAttribIndex()
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{
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// input_semantics[0]: semantic=1, hardware_mapping=4, size=2
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// If hardware_mapping were wrongly used as the attrib index, we'd read
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// attrib[4] instead of attrib[1] and get the wrong format/offset.
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const ulong memoryBase = 0x1_0000_0000;
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var memory = new FakeCpuMemory(memoryBase, 0x2000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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const ulong semanticsAddress = memoryBase + 0x100;
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const ulong attribTable = memoryBase + 0x200;
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const ulong bufferTable = memoryBase + 0x300;
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const ulong sharpBase = memoryBase + 0x800;
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// ShaderSemantic word: semantic=1, hw_mapping=4, size_in_elements=2
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WriteUInt32(memory, semanticsAddress, 1u | (4u << 8) | (2u << 16));
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// attrib[0] unused garbage
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WriteUInt32(memory, attribTable, 0xDEAD_BEEFu);
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// attrib[1]: buffer=0, format=k16_16Float(29), offset=8, fetch=0
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WriteUInt32(memory, attribTable + 4, 0u | (29u << 5) | (8u << 14));
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// V# at buffer table[0]: base=sharpBase, stride=16
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WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
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WriteUInt32(
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memory,
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bufferTable + 4,
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(uint)(sharpBase >> 32) | (16u << 16));
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var scalars = new uint[32];
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scalars[8] = (uint)(attribTable & 0xFFFF_FFFFUL);
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scalars[9] = (uint)(attribTable >> 32);
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scalars[10] = (uint)(bufferTable & 0xFFFF_FFFFUL);
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scalars[11] = (uint)(bufferTable >> 32);
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var tables = new AgcVertexMetadata.VertexTableRegisters(
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VertexBufferReg: 10,
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VertexAttribReg: 8,
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InputSemanticsCount: 1,
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InputSemanticsAddress: semanticsAddress);
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Assert.True(
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AgcVertexMetadata.TryBuildVertexResourcesFromMetadata(
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ctx,
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scalars,
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tables,
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out var resources));
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Assert.Single(resources);
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Assert.Equal(1u, resources[0].Semantic);
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Assert.Equal(4u, resources[0].HardwareMapping);
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Assert.Equal(8u, resources[0].OffsetBytes);
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Assert.Equal(5u, resources[0].DataFormat); // R16G16
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Assert.Equal(7u, resources[0].NumberFormat); // Float
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Assert.Equal(2u, resources[0].ComponentCount);
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Assert.Equal(sharpBase, resources[0].SharpBase);
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Assert.False(resources[0].PerInstance);
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}
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[Fact]
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public void MergeVertexInputs_OverlaysFormatWithoutRebasingCapture()
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{
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const ulong memoryBase = 0x1_0000_0000;
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var memory = new FakeCpuMemory(memoryBase, 0x2000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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const ulong semanticsAddress = memoryBase + 0x100;
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const ulong attribTable = memoryBase + 0x200;
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const ulong bufferTable = memoryBase + 0x300;
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const ulong sharpBase = memoryBase + 0x800;
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WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
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// format k8_8_8_8UNorm(56), offset=12
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WriteUInt32(memory, attribTable, 0u | (56u << 5) | (12u << 14));
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WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
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WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
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var scalars = new uint[32];
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scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
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scalars[5] = (uint)(attribTable >> 32);
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scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
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scalars[7] = (uint)(bufferTable >> 32);
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var tables = new AgcVertexMetadata.VertexTableRegisters(
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VertexBufferReg: 6,
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VertexAttribReg: 4,
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InputSemanticsCount: 1,
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InputSemanticsAddress: semanticsAddress);
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var data = new byte[64];
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var discovered = new[]
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{
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new Gen5VertexInputBinding(
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Pc: 0x40,
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Location: 0,
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ComponentCount: 4,
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DataFormat: 14, // wrong IR guess
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NumberFormat: 7,
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BaseAddress: sharpBase,
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Stride: 16,
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OffsetBytes: 0,
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Data: data,
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DataLength: data.Length,
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DataPooled: false),
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};
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var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
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ctx,
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scalars,
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tables,
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discovered);
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Assert.Single(merged);
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Assert.Equal(0u, merged[0].Location);
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Assert.Equal(sharpBase, merged[0].BaseAddress);
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Assert.Same(data, merged[0].Data);
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Assert.Equal(10u, merged[0].DataFormat); // RGBA8
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Assert.Equal(0u, merged[0].NumberFormat); // Unorm
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Assert.Equal(12u, merged[0].OffsetBytes);
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Assert.Equal(0x40u, merged[0].Pc);
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}
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[Fact]
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public void MergeVertexInputs_AcceptsVertexAttribFormatEnums()
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{
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// Attrib tables store VertexAttribFormat (227 = rgba8 unorm), not
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// BufferFormat (56). Without conversion the format patch is a no-op.
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const ulong memoryBase = 0x1_0000_0000;
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var memory = new FakeCpuMemory(memoryBase, 0x2000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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const ulong semanticsAddress = memoryBase + 0x100;
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const ulong attribTable = memoryBase + 0x200;
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const ulong bufferTable = memoryBase + 0x300;
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const ulong sharpBase = memoryBase + 0x800;
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WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
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WriteUInt32(memory, attribTable, 0u | (227u << 5) | (12u << 14)); // VertexAttribFormat
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WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
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WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
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var scalars = new uint[32];
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scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
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scalars[5] = (uint)(attribTable >> 32);
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scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
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scalars[7] = (uint)(bufferTable >> 32);
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var tables = new AgcVertexMetadata.VertexTableRegisters(
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VertexBufferReg: 6,
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VertexAttribReg: 4,
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InputSemanticsCount: 1,
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InputSemanticsAddress: semanticsAddress);
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var data = new byte[64];
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var discovered = new[]
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{
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new Gen5VertexInputBinding(
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0x40, 0, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
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};
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var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
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ctx,
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scalars,
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tables,
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discovered);
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Assert.Equal(10u, merged[0].DataFormat);
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Assert.Equal(0u, merged[0].NumberFormat);
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Assert.Equal(12u, merged[0].OffsetBytes);
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}
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[Fact]
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public void MergeVertexInputs_MatchesInterleavedAttrsByOffsetNotBareBase()
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{
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// Both attributes share SharpBase. Matching by base alone would assign
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// the color format to position (video/UI regression).
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const ulong memoryBase = 0x1_0000_0000;
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var memory = new FakeCpuMemory(memoryBase, 0x2000);
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var ctx = new CpuContext(memory, Generation.Gen5);
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const ulong semanticsAddress = memoryBase + 0x100;
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const ulong attribTable = memoryBase + 0x200;
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const ulong bufferTable = memoryBase + 0x300;
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const ulong sharpBase = memoryBase + 0x800;
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// semantic0 → pos float4 @0; semantic1 → color rgba8 @12
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WriteUInt32(memory, semanticsAddress, 0u | (0u << 8) | (4u << 16));
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WriteUInt32(memory, semanticsAddress + 4, 1u | (4u << 8) | (4u << 16));
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WriteUInt32(memory, attribTable, 0u | (77u << 5) | (0u << 14)); // k32_32_32_32Float
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WriteUInt32(memory, attribTable + 4, 0u | (56u << 5) | (12u << 14)); // rgba8unorm @12
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WriteUInt32(memory, bufferTable, (uint)(sharpBase & 0xFFFF_FFFFUL));
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WriteUInt32(memory, bufferTable + 4, (uint)(sharpBase >> 32) | (16u << 16));
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var scalars = new uint[32];
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scalars[4] = (uint)(attribTable & 0xFFFF_FFFFUL);
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scalars[5] = (uint)(attribTable >> 32);
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scalars[6] = (uint)(bufferTable & 0xFFFF_FFFFUL);
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scalars[7] = (uint)(bufferTable >> 32);
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var tables = new AgcVertexMetadata.VertexTableRegisters(
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VertexBufferReg: 6,
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VertexAttribReg: 4,
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InputSemanticsCount: 2,
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InputSemanticsAddress: semanticsAddress);
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var data = new byte[64];
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var discovered = new[]
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{
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new Gen5VertexInputBinding(
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0x40, 0, 4, 14, 7, sharpBase, 16, 0, data, data.Length, false),
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new Gen5VertexInputBinding(
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0x80, 1, 4, 14, 7, sharpBase, 16, 12, data, data.Length, false),
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};
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var merged = AgcVertexMetadata.MergeVertexInputsFromMetadata(
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ctx,
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scalars,
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tables,
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discovered);
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Assert.Equal(2, merged.Count);
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Assert.Equal(0u, merged[0].OffsetBytes);
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Assert.Equal(12u, merged[1].OffsetBytes);
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Assert.Equal(0u, merged[1].NumberFormat); // Unorm color, not float
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Assert.Equal(10u, merged[1].DataFormat); // RGBA8
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Assert.Equal(sharpBase, merged[0].BaseAddress);
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Assert.Equal(sharpBase, merged[1].BaseAddress);
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Assert.Same(data, merged[0].Data);
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}
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[Fact]
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public void CollectFetchPrologPcs_FindsSBufferLoadsFromTableRegisters()
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{
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var tables = new AgcVertexMetadata.VertexTableRegisters(
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VertexBufferReg: 10,
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VertexAttribReg: 8,
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InputSemanticsCount: 1,
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InputSemanticsAddress: 1);
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var program = new Gen5ShaderProgram(
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0,
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[
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new Gen5ShaderInstruction(
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0x10,
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Gen5ShaderEncoding.Smem,
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"SBufferLoadDword",
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Words: [],
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Sources: [Gen5Operand.Scalar(8)],
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Destinations: [Gen5Operand.Scalar(20)],
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new Gen5ScalarMemoryControl(1, 0, null)),
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new Gen5ShaderInstruction(
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0x20,
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Gen5ShaderEncoding.Smem,
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"SBufferLoadDword",
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Words: [],
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Sources: [Gen5Operand.Scalar(12)],
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Destinations: [Gen5Operand.Scalar(24)],
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new Gen5ScalarMemoryControl(1, 0, null)),
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new Gen5ShaderInstruction(
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0x30,
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Gen5ShaderEncoding.Sopp,
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"SEndpgm",
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Words: [],
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Sources: [],
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Destinations: [],
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null),
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]);
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var pcs = AgcVertexMetadata.CollectFetchPrologPcs(program, tables);
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Assert.Contains(0x10u, pcs);
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Assert.DoesNotContain(0x20u, pcs);
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}
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private static void WriteUInt32(FakeCpuMemory memory, ulong address, uint value)
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{
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Span<byte> bytes = stackalloc byte[4];
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BinaryPrimitives.WriteUInt32LittleEndian(bytes, value);
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Assert.True(memory.TryWrite(address, bytes));
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}
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}
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