From 61a97baf8543c667fabf1962f19cd00d755dcc91 Mon Sep 17 00:00:00 2001 From: Dafenx Date: Tue, 14 Jul 2026 16:11:11 +0200 Subject: [PATCH] [AGC] Emit Gen5 v_sad_u32 (#138) Co-authored-by: Dafenx <196083014+Dafenxz0@users.noreply.github.com> --- src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs b/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs index dc0437ff..d95ddc3a 100644 --- a/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs +++ b/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs @@ -601,6 +601,18 @@ internal static partial class Gen5SpirvTranslator Ext(38, _uintType, high, right)); break; } + case "VSadU32": + { + var left = GetRawSource(instruction, 0); + var right = GetRawSource(instruction, 1); + var difference = _module.AddInstruction( + SpirvOp.ISub, + _uintType, + Ext(41, _uintType, left, right), + Ext(38, _uintType, left, right)); + result = IAdd(difference, GetRawSource(instruction, 2)); + break; + } case "VMed3I32": { var left = Bitcast(_intType, GetRawSource(instruction, 0));