diff --git a/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs b/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs index cfb4c7e..7337969 100644 --- a/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs +++ b/src/SharpEmu.Libs/Agc/Gen5ShaderTranslator.cs @@ -900,6 +900,7 @@ internal static class Gen5ShaderTranslator 0x169 => "VMulLoU32", 0x16A => "VMulHiU32", 0x16B => "VMulLoI32", + 0x16C => "VMulHiI32", 0x360 => "VMadU32U16", 0x361 => "VMulLoU32", 0x362 => "VLdexpF32", diff --git a/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs b/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs index 9df8d40..2d8d3c7 100644 --- a/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs +++ b/src/SharpEmu.Libs/Agc/Gen5SpirvTranslator.Alu.cs @@ -337,6 +337,7 @@ internal static partial class Gen5SpirvTranslator result = EmitSubtractWithBorrow(instruction, reverse: true); break; case "VMulLoU32": + case "VMulLoI32": case "VMulU32U24": result = EmitIntegerBinary(instruction, SpirvOp.IMul); break; @@ -372,6 +373,29 @@ internal static partial class Gen5SpirvTranslator _module.Constant64(_ulongType, 32))); break; } + case "VMulHiI32": + { + var wideLeft = _module.AddInstruction( + SpirvOp.SConvert, + _longType, + Bitcast(_intType, GetRawSource(instruction, 0))); + var wideRight = _module.AddInstruction( + SpirvOp.SConvert, + _longType, + Bitcast(_intType, GetRawSource(instruction, 1))); + var product = _module.AddInstruction( + SpirvOp.IMul, + _longType, + wideLeft, + wideRight); + result = _module.AddInstruction( + SpirvOp.UConvert, + _uintType, + ShiftRightLogical64( + Bitcast(_ulongType, product), + _module.Constant64(_ulongType, 32))); + break; + } case "VMadU32U24": { var left = BitwiseAnd(